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PDF ( 数据手册 , 数据表 ) IQX240B

零件编号 IQX240B
描述 IQX Series
制造商 I-CUBE
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IQX240B 数据手册, 描述, 功能
et4U.com IQX Family Data SheetFEATURES
heSRAM-based, in-system programmable
taSSwitch Matrix
a— Non-Blocking
.D— Identical and predictable delays
— One-to-one, one-to-many and many-to-one connections
wwRapidConfigure™ parallel interface for fast, incremental
w configuration of Switch Matrix and I/O Port attributes
m— 100% JTAG compliant
Clocked, Latched and Flow-through Dataflow Modes
o— As low as 7.5 ns pin-to-pin delay in flow-through mode
.cand 133 MHz clock rate in registered mode
I/O Ports
— Individually programmable as input, output or
Ubidirectional
t4— For each I/O Port, clock, clock enable, input enable and
output enable can be selected independently from a large
epool of common control signals
— 12 mA current drive
e— Separated I/O power pins for easy interfacing between
h5V and 3.3V signals
DESCRIPTION
The IQX family of SRAM-based bit-oriented switching devices is
manufactured using a 0.6µ m CMOS process. These devices
offer clock speeds of up to 133 MHz and pin-to-pin delay as low
as 7.5 ns.
The IQX devices are used in applications requiring dynamic
switching and flexible routing / interconnection of signals. These
applications include communication switches, network systems,
DSP / image processing engines and file/video servers.
At the heart of IQX devices is a non-blocking Switch Matrix. A
line in the Switch Matrix can be connected to one or more other
lines. The Switch Matrix lines are connected to I/O Ports with
programmable functional attributes.
The RapidConfigure parallel interface allows connections in the
Switch Matrix to be changed quickly and incrementally. This
interface can also be used to configure I/O Port attributes
individually and incrementally. In either case, data integrity is
maintained on all unchanged signal paths through the device.
The IQX devices support the industry standard JTAG (IEEE
1149.1) interface for boundary scan testing. The same interface
can also used for serially downloading the configuration bit
stream into the devices.
taSShared with
aI/O Control
Signals
I/O Port
I/O Port
.DI/O Port
I/O Port
www omShared with
.cRapidConfigure
t4UInterface Signals
I/O Port
I/O Port
I/O Port
Dedicated
I/O Control Signals
I/O
Control
Signal
Ports
Switch Matrix
[Crossbar Array]
RapidConfigure
Interface
JTAG Configuration Control
heeTDO TDI TMS TCK TRST*
taSFigure 1. IQX Functional Block Diagram
www.DaJune 2000
Revision 5.0
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IQX240B pdf, 数据表
Tables
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IQX240B equivalent, schematic
IQX Family Data Sheet
2, 4, 8 or 16 I/O Ports (having the same configuration) can be
configured in a minimum of one or maximum of eight
RapidConfigure cycles.
The RapidConfigure interface shown in Figure 7 is a write only
interface. Its operation is some what similar to a memory write
cycle in a microprocessor system - it uses address, data and
control signals to write to the Switch Matrix SRAM cells and I/O
Port configuration registers. The Control bus, {P/S (Port/Switch),
C[1:0]} defines the type of operation performed by the
RapidConfigure cycle, while the Row Address, RA[m-1:0], and
Column Address, CA[m-1:0], provide the necessary addresses
and/or data for the different operations. The value “m” is different
for different devices as shown in Table 2. WE (Write Enable)
acts as chip select while STROBE is the write strobe.
Feature
Total Number of I/O
Ports
I/O Ports Used for RC
Interface1
Row Address and
Column Address Bus
Widths
I/O Ports whose
connections can be
changed using RC
interface2
IQX320
320
23 / 22
9
298
IQX240B
240
23 / 22
9
218
IQX160
160
21/20
8
140
IQX128B
128
19/18
7
102
Table 2. RapidConfigure Interface Pin Count
Notes:
1. The IQ compatibility mode uses the lower of the two numbers shown.
2. Due to the requirements for compatibility with the IQ Family and/or
bondout restrictions, this number is lower than (# in row 1 - #
in row 2) for some devices.
DATA
BUS
ADDRESS
BUS
CPU
CLK Config
Control
Logic
CA[m-1:0]
RA[m-1:0]
IQX
RCE
C0
C1
P/S
WE
STROBE
TRST* TDI TMS TCK
I/O Port
I/O Port
I/O Port
Optional
Figure 7. IQX RapidConfigure System Interface
In a typical system, an embedded processor will compute the
required Row Address, Column Address and Control values and
apply them to the IQX device. Alternatively, these values could
be computed before hand using the I-Cube supplied
development system software (IDS100), and stored in a lookup
table.
The RapidConfigure mode is enabled or disabled by correctly
setting the RC bit in the Mode Control Register. Table 3 shows
the different RapidConfigure options, depending on the values of
the “RC” and “RM” bits in the Mode Control Register. During
hardware reset (TRST* = 0) these bits are set to the signal value
on the “RCE” (RapidConnect Enable) pin. The values of these
bits can then be changed if required using the JTAG serial
interface. Note that the “P/S” signal shown in Figure 7 is required
only if the RapidConfigure interface is used for changing I/O Port
configuration, i.e., when RC bit = 1 and RM bit = 1. The pin is
available for use as signal I/O pin (I/O Port) when RM bit = 0.
Table 8 summarizes the different options. Compatibility with the
IQ family devices is achieved by connecting the RCE pin to VSS
on the board.
RC Bit RM Bit
Operation
0 0 RapidConfigure Mode is disabled. The device can only be
configured using the JTAG-based serial interface. In this
mode, the I/O Ports used for RapidConfigure Interface can
be used for as signal I/O Ports.
1 0 RapidConfigure Mode is enabled for changing Switch
Matrix connections but not for I/O Port configuration. The
I/O Ports can only be configured using the JTAG-based
serial interface.
In this mode, the signal coming from the P/S pin is forced
low internally. The P/S pin is available as a signal I/O Port.
1 1 RapidConfigure Mode is enabled for changing Switch
Matrix connections and I/O Port configurations.
Table 3. RapidConfigure Options
The user must ensure that the I/O Ports used for the
RapidConfigure interface are in the Input (IN) mode and any
connections to corresponding signal lines in the Switch Matrix
are cleared before attempting to configure the device using this
interface. During device reset, the I/O Ports used for the
RapidConfigure interface are set to the required Input (IN) and
all connections in the Switch Matrix are cleared.
1.4.1 Switch Matrix Connection Changes
As indicated earlier, the Switch Matrix SRAM cells that control
the connections among I/O Ports form a two dimensional array.
Every SRAM cell location in the Switch Matrix that is being
written to is uniquely identified by its Row (or Word) Address and
Column (or Bit) Address. The real SRAM cell responsible for the
connection between two I/O Port numbers “i” and “j” on the
16
Revision 5.0
June 2000










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