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PDF ( 数据手册 , 数据表 ) C8051F332

零件编号 C8051F332
描述 (C8051F330 - C8051F335) Mixed Signal ISP Flash MCU
制造商 Silicon Laboratories
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C8051F332 数据手册, 描述, 功能
Analog Peripherals
- 10-Bit ADC (‘F330/2/4 only)
Up to 200 ksps
Up to 16 external single-ended or differential inputs
VREF from internal VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- 10-Bit Current Output DAC (‘F330 only)
- Comparator
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (0.4 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.4 mA at 25 MHz;
9 µA at 32 kHz
- Typical stop mode current: 0.1 µA
Temperature Range: –40 to +85 °C
C8051F330/1/2/3/4/5
Mixed-Signal ISP Flash MCU
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 768 bytes internal data RAM (256 + 512)
- 8 kB (‘F330/1), 4 kB (‘F332/3), or 2 kB (‘F334/5)
Flash; In-system programmable in 512-byte Sec-
tors—512 bytes are reserved in the 8 kB devices
Digital Peripherals
- 17 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with three
capture/compare modules
- Real time clock mode using PCA or timer and exter-
nal clock source
Clock Sources
- Two internal oscillators:
24.5 MHz with ±2% accuracy supports crystal-less
UART operation
80/40/20/10 kHz low frequency, low power
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
20-Pin QFN Package
ANALOG
PERIPHERALS
A
10-bit
10-bit
M
U
200 ksps
Current
DAC
X
ADC
‘F330 only
TEMP
SENSOR
‘F330/2/4 only
+
-
VOLTAGE
COMPARATOR
DIGITAL I/O
UART
SMBus
Port 0
SPI
PCA
Port 1
Timer 0
Timer 1
P2.0
Timer 2
Timer 3
24.5 MHz PRECISION
INTERNAL OSCILLATOR
LOW FREQUENCY INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
2/4/8 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR WDT
Rev. 1.7 12/10
Copyright © 2010 by Silicon Laboratories
C8051F330/1/2/3/4/5







C8051F332 pdf, 数据表
C8051F330/1/2/3/4/5
Figure 10.2. Power-On and VDD Monitor Reset Timing .......................................... 98
11. Flash Memory
Figure 11.1. Flash Program Memory Map.............................................................. 105
12. External RAM
13. Oscillators
Figure 13.1. Oscillator Diagram.............................................................................. 113
Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 119
14. Port Input/Output
Figure 14.1. Port I/O Functional Block Diagram ..................................................... 123
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 124
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped ............................... 125
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 126
15. SMBus
Figure 15.1. SMBus Block Diagram ....................................................................... 135
Figure 15.2. Typical SMBus Configuration ............................................................. 136
Figure 15.3. SMBus Transaction ............................................................................ 137
Figure 15.4. Typical SMBus SCL Generation......................................................... 141
Figure 15.5. Typical Master Transmitter Sequence................................................ 147
Figure 15.6. Typical Master Receiver Sequence.................................................... 148
Figure 15.7. Typical Slave Receiver Sequence...................................................... 149
Figure 15.8. Typical Slave Transmitter Sequence.................................................. 150
16. UART0
Figure 16.1. UART0 Block Diagram ....................................................................... 153
Figure 16.2. UART0 Baud Rate Logic .................................................................... 154
Figure 16.3. UART Interconnect Diagram .............................................................. 155
Figure 16.4. 8-Bit UART Timing Diagram............................................................... 155
Figure 16.5. 9-Bit UART Timing Diagram............................................................... 156
Figure 16.6. UART Multi-Processor Mode Interconnect Diagram .......................... 157
17. Enhanced Serial Peripheral Interface (SPI0)
Figure 17.1. SPI Block Diagram ............................................................................. 163
Figure 17.2. Multiple-Master Mode Connection Diagram ....................................... 166
Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram166
Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram166
Figure 17.5. Master Mode Data/Clock Timing ........................................................ 168
Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 169
Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 169
Figure 17.8. SPI Master Timing (CKPHA = 0)........................................................ 173
Figure 17.9. SPI Master Timing (CKPHA = 1)........................................................ 173
Figure 17.10. SPI Slave Timing (CKPHA = 0)........................................................ 174
Figure 17.11. SPI Slave Timing (CKPHA = 1)........................................................ 174
18. Timers
Figure 18.1. T0 Mode 0 Block Diagram.................................................................. 178
Figure 18.2. T0 Mode 2 Block Diagram.................................................................. 179
8 Rev. 1.7







C8051F332 equivalent, schematic
C8051F330/1/2/3/4/5
16 Rev. 1.7










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