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PDF ( 数据手册 , 数据表 ) KM29U64000IT

零件编号 KM29U64000IT
描述 8M x 8 Bit NAND Flash Memory
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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KM29U64000IT 数据手册, 描述, 功能
KM29U64000T, KM29U64000IT
Document Title
8M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 Data Sheet, 1998
1.1 Data Sheet. 1999
1) Added CE dont’ care mode during the data-loading and reading
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
Remark
Preliminary
Final
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the
SAMSUNG branch office near you.
1







KM29U64000IT pdf, 数据表
KM29U64000T, KM29U64000IT
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
CLE Set-up Time
tCLS
0
CLE Hold Time
tCLH
10
CE Setup Time
tCS 0
CE Hold Time
tCH 10
WE Pulse Width
tWP 25
ALE Setup Time
ALE Hold Time
tALS
tALH
0
10
Data Setup Time
tDS 20
Data Hold Time
tDH 10
Write Cycle Time
tWC 50
WE High Hold Time
tWH 15
Max
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay( ID read )
ALE to RE Delay(Read cycle)
CE to RE Delay( ID read)
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
RE Access Time
RE High to Output Hi-Z
CE High to Output Hi-Z
RE High Hold Time
Output Hi-Z to RE Low
Last RE High to Busy(at sequential read)
CE High to Ready(in case of interception by CE at read)(1)
CE High Hold Time(at the last serial read)(3)
RE Low to Status Output
CE Low to Status Output
WE High to RE Low
RE access time(Read ID)
Device Resetting Time(Read/Program/Erase)
Symbol
tR
tAR1
tAR2
tCR
tRR
tRP
tWB
tRC
tREA
tRHZ
tCHZ
tREH
tIR
tRB
tCRY
tCEH
tRSTO
tCSTO
tWHR
tREADID
tRST
NOTE : 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to VOL.
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
3. To break the sequential read cycle, CE must be held high for longer time than tCEH.
Min Max Unit
-7
100 -
µs
ns
50 - ns
100 -
ns
20 - ns
30 - ns
- 100 ns
50 - ns
- 35 ns
15 30 ns
- 20 ns
15 - ns
0 - ns
- 100 ns
-
50 +tr(R/B)(2)
ns
100 -
ns
- 35 ns
- 45 ns
60 - ns
- 35 ns
-
5/10/500
µs
8







KM29U64000IT equivalent, schematic
KM29U64000T, KM29U64000IT
* Status Read Cycle
FLASH MEMORY
CLE
CE
WE
RE
I/O0 ~ 7
tCLS
tCS
tCLH
tCLS
tCH
tWP
tWHR
tCSTO
tCHZ
tDS tDH
70H
tIR tRSTO
tRHZ
Status Output
READ1 OPERATION(READ ONE PAGE)
CLE
CE
WE
ALE
RE
I/O0 ~ 7
R/B
tWC
tWB
tAR2
tR tRC
tRR
00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A22
Column
Address
Page(Row)
Address
Busy
Dout N Dout N+1 Dout N+2 Dout N+3
16
tCEH
tCHZ
tCRY
tRHZ
Dout 527
tRB










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