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PDF ( 数据手册 , 数据表 ) IN24LC08

零件编号 IN24LC08
描述 (IN24LC04/08) 8K 2.5V CMOS Serial EEPROMs
制造商 IK Semiconductor
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IN24LC08 数据手册, 描述, 功能
TECHNICAL DATA
4K/8K 2.5V CMOS Serial EEPROMs
IN24LC04/08
DESCRIPTION
IN24LC04/08 is a 4K-or 8K-bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x 8
bit memory with a two wire serial interface. Low voltage design permits operation down to 2.5 volts with standby and
active currents of only 5µA and 1mA respectively. The IN24LC04/08 also has a page-write capability for up to 16
bytes of data. The IN24LC04B/08B is available in the standard 8-pin DIP.
FEATURES
m• Single supply with operation down to 2.5V
o• Low power CMOS technology
.c- 1 mA active current typical
- 10 µA standby current typical at 5.5V
U- 5 µA standby current typical at 3.0V
t4• Organized as two or four blocks of 256 bytes (2x256x8) and
(4x256x8)
e• Two wire serial interface bus, I2C compatible
e• Schmitt trigger, filtered inputs for noise suppression
h• Output slope control to eliminate ground bounce
S• 100 kHz (2.5V) and 400 kHz (5V) compatibility
ta• Self-timed write cycle (including auto-erase)
a• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
.D• Hardware write protect for entire memory
• Can be operated as a serial ROM
w• Factory programming (QTP) available
w• ESD protection > 4,000V
w• 1,000,000 ERASE/WRITE cycles guaranteed*
PACKAGE
TA = -40 ... +85 °C
Name
PINNING
Function
Vss Ground
SDA
Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
VCC
+2.5V to 5.5V Power Supply
AO, A1, A2 No Internal Connection
Pin Connection
• Data retention > 200 years
• 8-pin DIP
A0 1
8 Vcc
• Temperature range -40 to +85 oC
A1 2
7 WP
A2 3
6 SCL
Vss 4
5 SDA
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IN24LC08 pdf, 数据表
Figure 8. Page Write
IN24LC04/08
Figure 9. Current Address Read
Figure 10. Random Read
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the IN24LC04/08
transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a
random read. This directs the IN24LC04/08 to transmit the next sequentially addressed 8 bit word
(see Figure 11).
To provide sequential reads the IN24LC04/08 contains an internal address pointer which is
incremented by one at the completion of each operation. This address pointer allows the entire
memory contents to be serially read during one operation.
Noise Protection
The IN24LC04/08 employs a Vcc threshold detector circuit which disables the internal erase/write
logic if the Vcc is below 1,5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to
assure proper device operation even on a noisy bus.
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