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PDF ( 数据手册 , 数据表 ) U6813B

零件编号 U6813B
描述 Fail-safe IC with High-side and Relay Driver
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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U6813B 数据手册, 描述, 功能
Features
Digital Self-supervising Watchdog with Hysteresis
One 150-mA Output Driver for Relay
One High-side Driver for N-channel Power FET
Positive and Negative Enable Output
Positive and Negative Reset Output
Over/Under-voltage Detection
Relay and Power FET Outputs Protected Against Standard Transients and 55-V Load
Dump
Description
The function of microcontrollers in safety-critical applications (e.g., anti-lock systems)
needs to be monitored permanently. Usually, this task is accomplished by an indepen-
dent watchdog timer. The monolithic IC U6813B, designed in bipolar technology and
qualified according to the needs of the automotive industry, includes such a watchdog
timer and provides additional features for added value. With the help of integrated
driver stages, it is easy to control safety-related functions of a relay and of an N-chan-
nel power MOSFET in high-side applications. In case of a microcontroller malfunction
or supply-voltage anomalies, the U6813B provides positive and negative reset and
enable output signals. This flexibility guarantees a broad range of applications. The
U6813B is based on of Atmel’s fail-safe ICs U6808B and U6809B.
Figure 1. Block Diagram
Fail-safe IC with
High-side and
Relay Driver
U6813B
3.3 V 16
VCC 14
3.3-V under- and
overvoltage detect.
Bandgap
reference
2.44 V
Reset
debounce
fosc
Power-on
reset
Reset
delay
fosc
RELI 13
FETI 12
WDI 11
5-V under- and
overvoltage detect.
19k
19k
Watchdog
19k
15
SGND
2
GND
Internal
oscillator
fosc
RC-
oscillator
supervisor
RC
oscillator
10
WDC
VCC
3 P-RES
4 N-RES
Current
limitation
VCC
VCC
FET
output
8 CAPI
1 RELO
6 N-EN
5 P-EN
9 FETO
7 VS
Rev. 4543A–AUTO–05/02
1







U6813B pdf, 数据表
Electrical Characteristics (Continued)
VCC = 5 V, Tamb = -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection);
fintern = 200 kHz +50%/-45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at Pin CAPI
No. Parameters
Test Conditions
Pin Symbol Min. Typ. Max. Unit
Type*
8 Digital Output P-EN (Internal Pull-up Resistor)
8.1 Saturation voltage
high
I £ 3 mA
5 VSAT5
0.5 V
A
8.2 Leakage current
8.3 Internal pull-up
resistor
at 5 V, high state
at 0 V
5 ILEAK5
5
RINT5
12.5
0.5 mA
50 kW
A
A
8.4 Enable debounce
Over- or undervoltage
time (switch to high)
5
tDEB5
120 320 500
ms
A
8.5 Enable delay (switch Over- or undervoltage
back to low)
5
tDEL5
85 ms A
9 Relay Driver (RELO)
9.1 Saturation voltage
9.2 Current limitation
9.3 Internal clamping
voltage
I £ 150 mA
1 VSAT1 0.1
1 ILIM 150
1 VCL 26
0.5 V
300 mA
30 V
A
A
A
9.4 Turn-off energy
1 30
mJ C
9.5 Leakage current
VBatt = 16 V
VBatt = 26 V at 25°C
1
ILEAK1
ILEAK1
20 mA
200 mA
A
10 Power-FET Output FETO (Maximum Load Capacitor at FET Gate 470 pF, Charge-pump Frequency 110 to 300 kHz)
10.1 Output voltage
VS = 9 V to 15 V
9
VOUT9
VS +
10 V
VS +
15 V
V
A
10.2 Operation range
10.3 Overvoltage shut-
down
7 VS
9
7 VS 20
20 V
24 V
A
A
10.4 Internal clamping
voltage
9 VCL 26
30 V
A
10.5 On/off frequency
9f
200 Hz
A
10.6 Maximum current
11 Battery Supply
FETO
9 IFETO 10
mA A
11.1 Internal clamping
voltage
7 VCL 26
30 V
A
11.2 Clamping current
capability (1)
7 IVS
5
mA A
11.3 Leakage current
at FETI = low
7 ILEAVS
100 mA
12 Reset and VCC Control
12.1 Lower reset level
Reference SGND
14 VCC
4.5
4.75 V
12.2 Upper reset level
Reference SGND
14 VCC 5.25
5.5 V
12.3 Hysteresis
14 VHYST14
25
100 mV
12.4 Reset debounce time
14
tDEB
120 320 500
ms
12.5 Reset delay
14 tDEL
20 50 80 ms
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor.
A
A
A
A
A
A
8 U6813B
4543A–AUTO–05/02














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