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PDF ( 数据手册 , 数据表 ) ST6201C

零件编号 ST6201C
描述 8-BIT MCU
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


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ST6201C 数据手册, 描述, 功能
ST6200C ST6201C ST6203C
8-bit MCUs with A/D converter,
two timers, oscillator safeguard & safe reset
Memories
– 1K or 2K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
– 64 bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system
– Low voltage detector (LVD) for safe Reset
– Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
– Oscillator safeguard (OSG)
– 2 Power saving modes: Wait and Stop
Interrupt Management
– 4 interrupt vectors plus NMI and RESET
– 9 external interrupt lines (on 2 vectors)
9 I/O Ports
– 9 multifunctional bidirectional I/O lines
– 4 alternate function lines
– 3 high sink outputs (20mA)
2 Timers
– Configurable watchdog timer
– 8-bit timer/counter with a 7-bit prescaler
Analog Peripheral
– 8-bit ADC with 4 input channels (except on
ST6203C)
Instruction Set
– 8-bit data manipulation
– 40 basic instructions
– 9 addressing modes
– Bit manipulation
PDIP16
SO16
SSOP16
CDIP16W
(See Section 11.5 for Ordering Information)
Development Tools
– Full hardware/software development package
Device Summary
Features
ST6200C
ST6201C
ST6203C
Program memory - bytes
1K
2K
RAM - bytes
Operating Supply
64
3.0V to 6V
Analog Inputs
4
Clock Frequency
Operating Temperature
Packages
8MHz Max
-40°C to +125°C
PDIP16 / SO16 / SSOP16
1K
-
October 2009
Doc ID 4563 Rev 5
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ST6201C pdf, 数据表
ST6200C ST6201C ST6203C
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES
3.1 MEMORY AND REGISTER MAPS
3.1.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
000h
PROGRAM SPACE
PROGRAM
MEMORY
(see Figure 4)
0FF0h
0FFFh
INTERRUPT &
RESET VECTORS
000h
DATA SPACE
RESERVED
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0BFh
0C0h
0FFh
DATA ROM
WINDOW
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
HARDWARE
CONTROL
REGISTERS
(see Table 2)
ACCUMULATOR
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Doc ID 4563 Rev 5







ST6201C equivalent, schematic
ST6200C ST6201C ST6203C
4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses.
4.2 MAIN FEATURES
40 basic instructions
9 main addressing modes
Two 8-bit index registers
Two 8-bit short direct registers
Low power modes
Maskable hardware interrupts
6-level hardware stack
4.3 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
Space as a RAM location at address FFh. Thus
the ST6 can manipulate the accumulator just like
any other register in Data Space.
Index Registers (X, Y). These two registers are
used in Indirect addressing mode as pointers to
memory locations in Data Space. They can also
be accessed in Direct, Short Direct, or Bit Direct
addressing modes. They are mapped in Data
Space at addresses 80h (X) and 81h (Y) and can
be accessed like any other memory location.
Short Direct Registers (V, W). These two regis-
ters are used in Short Direct addressing mode.
This means that the data stored in V or W can be
accessed with a one-byte instruction (four CPU cy-
cles). V and W can also be accessed using Direct
and Bit Direct addressing modes. They are
mapped in Data Space at addresses 82h (V) and
83h (W) and can be accessed like any other mem-
ory location.
Note: The X and Y registers can also be used as
Short Direct registers in the same way as V and W.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next instruction to be executed by the core. This
ROM location may be an opcode, an operand, or
the address of an operand.
Figure 7. CPU Registers
7
0
RESET VALUE = xxh
70
RESET VALUE = xxh
70
RESET VALUE = xxh
70
RESET VALUE = xxh
70
RESET VALUE = xxh
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
V SHORT INDIRECT
REGISTER
W SHORT INDIRECT
REGISTER
SIX LEVEL
STACK
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
CN ZN
CI ZI
CNMI ZNMI
11 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh
x = Undefined value
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