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PDF ( 数据手册 , 数据表 ) TE28F016B3xxx

零件编号 TE28F016B3xxx
描述 (TE28F Series) SMART 3 ADVANCED BOOT BLOCK 4-8-16-32-MBIT FLASH MEMORY FAMILY
制造商 Intel
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TE28F016B3xxx 数据手册, 描述, 功能
E
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
4-, 8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3
28F008B3, 28F016B3, 28F032B3
n Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
12 V VPP Fast Production
Programming
n 2.7 V or 1.65 V I/O Option
Reduces Overall System Power
n High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n Optimized Block Sizes
Eight 8-KB Blocks for Data,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks for
Code
n Block Locking
VCC-Level Control through WP#
n Low Power Consumption
10 mA Typical Read Current
n Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n Extended Temperature Operation
–40 °C to +85 °C
n Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., Voice)
n Automated Program and Block Erase
Status Registers
n Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles Guaranteed
n Automatic Power Savings Feature
Typical ICCS after Bus Inactivity
n Standard Surface Mount Packaging
48-Ball µBGA* Package
48-Lead TSOP Package
40-Lead TSOP Package
n Footprint Upgradeable
Upgrade Path for 4-, 8-, 16-, and 32-
Mbit Densities
n ETOX™ VI (0.25 µ) Flash Technology
The Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a feature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and
interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single
device. Add to this the Intel-developed Flash Data Integrator (FDI) software, and you have a cost-effective,
monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40-
lead and 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s WWW page: http://www.intel.com/design/flash.
July 1998
Order Number: 290580-005







TE28F016B3xxx pdf, 数据表
SMART 3 ADVANCED BOOT BLOCK
E
1
A A14
B A15
C A16
23456
16M
A12 A8 VPP WP# A20
8M
A10 WE# RP# A19
A18
A13 A9
32M
A21
A6
7
A7
A5
A3
8
A4
A2
A1
D A17
NC
D5
NC
D2
NC CE#
A0
E VCCQ
A11
D6
NC
D3
NC
D0 GND
F GND
D7
NC
D4
VCC NC
D1 OE#
0580_04
NOTE:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A20 is the upgrade address for the 16-Mbit device. A21 is the
upgrade address for the 32-Mbit device.
2. 4-Mbit density not available in µBGA* CSP.
Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
8 PRELIMINARY







TE28F016B3xxx equivalent, schematic
SMART 3 ADVANCED BOOT BLOCK
E
3.2.3
READ STATUS REGISTER
The device status register indicates when a
program or erase operation is complete and the
success or failure of that operation. To read the
status register issue the Read Status Register
(70H) command to the CUI. This causes all
subsequent read operations to output data from the
status register until another command is written to
the CUI. To return to reading from the array, issue
the Read Array (FFH) command.
The status register bits are output on DQ0–DQ7.
The upper byte, DQ8–DQ15, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on
the falling edge of OE# or CE#. This prevents
possible bus errors which might occur if status
register contents change while being read. CE# or
OE# must be toggled with each subsequent status
read, or the status register will not indicate
completion of a program or erase operation.
When the WSM is active, SR.7 will indicate the
status of the WSM; the remaining bits in the status
register indicate whether or not the WSM was
successful in performing the desired operation (see
Table 7).
3.2.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and
clears bits 2, 6 and 7 to “0,” but cannot clear status
bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and
5 indicate various error conditions, these bits can
only be cleared through the Clear Status Register
(50H) command. By allowing the system software
to control the resetting of these bits, several
operations may be performed (such as cumulatively
programming several addresses or erasing multiple
blocks in sequence) before reading the status
register to determine if an error occurred during that
series. Clear the status register before beginning
another command or sequence. Note, again, that
the Read Array command must be issued before
data can be read from the memory array.
3.2.4
PROGRAM MODE
Programming is executed using a two-write
sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to program desired bits of the
addressed location, then Verify the bits are
sufficiently programmed. Programming the memory
results in specific bits within an address location
being changed to a “0.” If the user attempts to
program “1”s, the memory cell contents do not
change and no error occurs.
The status register indicates programming status:
while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling
either CE# or OE#. While programming, the only
valid commands are Read Status Register,
Program Suspend, and Program Resume.
When programming is complete, the Program
Status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status
register is set to indicate a program failure. If SR.3
is set then VPP was not within acceptable limits, and
the WSM did not execute the program command. If
SR.1 is set, a program operation was attempted on
a locked block and the operation was aborted.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, to prevent inadvertent status register
reads, be sure to reset the CUI to read array mode.
3.2.4.1
Suspending and Resuming
Program
The Program Suspend halts the in-progress
program operation to read data from another
location of memory. Once the programming process
starts, writing the Program Suspend command to
the CUI requests that the WSM suspend the
program sequence (at predetermined points in the
program algorithm). The device continues to output
status register data after the Program Suspend
command is written. Polling status register bits
SR.7 and SR.2 will determine when the program
operation has been suspended (both will be set to
“1”). tWHRH1/tEHRH1 specify the program suspend
latency.
16 PRELIMINARY










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