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PDF ( 数据手册 , 数据表 ) ST95P08

零件编号 ST95P08
描述 8 Kbit Serial SPI EEPROM with Positive Clock Strobe
制造商 ST Microelectronics
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ST95P08 数据手册, 描述, 功能
ST95P08
8 Kbit Serial SPI EEPROM with Positive Clock Strobe
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE 3V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
DESCRIPTION
The ST95P08 is an 8 Kbit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. The 8 Kbit memory
is organised as 64 pages of 16 bytes. The memory
is accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q). The device connected to the bus is selected
when the chip select input (S) goes low. Commu-
nications with the chip can be interrupted with a
hold input (HOLD). The write operation is disabled
by a write protect input (W).
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
Figure 1. Logic Diagram
VCC
D
C
S
W
HOLD
ST95P08
VSS
February 1999
Q
AI01315
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ST95P08 pdf, 数据表
ST95P08
Read Status Register (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any
time, even during a non-volatile write. As soon as
the 8th bit of the status register is read out, the
ST95P08 enters a wait mode (data on D are not
decoded, Q is in Hi-Z) until it is deselected.
The status register format is as follows:
b7 b0
1 1 1 1 BP1 BP0 WEL WIP
BP1, BP0: Read and write bits
WEL, WIP: Read only bits.
During a non-volatile write to the memory array, all
bits BP1, BP0, WEL, WIP are valid and can be read.
During a non volatile write to the status register, the
only bits WEL and WIP are valid and can be read.
The values of BP1 and BP0 read at that time
correspond to the previous contents of the status
register.
The Write-In-Process (WIP) read only bit indicates
whether the ST95P08 is busy with a write opera-
tion. When set to a ’1’ a write is in progress, when
set to a ’0’ no write is in progress.
The Write Enable Latch (WEL) read only bit indi-
cates the status of the write enable latch. When set
to a ’1’ the latch is set, when set to a ’0’ the latch is
reset.
The Block Protect (BP0 and BP1) bits indicate the
extent of the protection employed. These bits are
set by the user issuing the WRSR instruction.
These bits are non-volatile.
Write Status Register (WRSR)
The WRSR instruction allows the user to select the
size of protected memory. The ST95P08 is divided
into four 2048 bit blocks. The user may read the
blocks but will be unable to write within the selected
blocks.
The blocks and respective WRSR control bits are
shown in Table 6.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S. This
rising edge of S must appear after the 8th bit of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Read Operation
The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 and 4 of the
read instruction contain address bits A9 and A8
(most significant address bits). These bits are used
to select the first or second page of the device.
Then, the data stored in the memory at the selected
address is shifted out on the Q output pin; each bit
being shifted out during the falling edge of the clock
(C). The data stored in the memory at the next
address can be read in sequence by continuing to
provide clock pulses. The byte address is automat-
Table 7. Array Addresses Protect
Status Register Bits
BP1
BP0
Array Addresses
Protected
00
none
01
300h - 3FFh
10
200h - 3FFh
11
000h - 3FFh
Table 8. Instruction Set
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Notes: A = 1, Upper page selected
A = 0, Lower page selected
X = Don’t care
8/16
Description
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Instruction Format
000X X110
000X X100
000X X101
000X X001
000A A011
000A A010







ST95P08 equivalent, schematic
ST95P08
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners
STMicroelectronics GROUP OF COMPANIES
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