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PDF ( 数据手册 , 数据表 ) UDA1328T

零件编号 UDA1328T
描述 Multi-channel filter DAC
制造商 NXP Semiconductors
LOGO NXP Semiconductors LOGO 


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UDA1328T 数据手册, 描述, 功能
INTEGRATED CIRCUITS
DATA SHEET
UDA1328T
Multi-channel filter DAC
Product specification
Supersedes data of 2000 Jan 04
File under Integrated Circuits, IC01
2001 Mar 27







UDA1328T pdf, 数据表
Philips Semiconductors
Multi-channel filter DAC
Product specification
UDA1328T
8.7.2 DE-EMPHASIS CONTROL
In static pin mode the pins DEEM0 and DEEM1 control the
de-emphasis mode; see Table 3.
Table 3 De-emphasis control
DEEM MODE
No de-emphasis
32 kHz de-emphasis
44.1 kHz de-emphasis
48 kHz de-emphasis
DEEM1
0
0
1
1
DEEM0
0
1
0
1
8.7.3 DIGITAL INTERFACE FORMATS
In static pin mode the digital audio interface formats can be
selected via pin 17 (SF1) and 19 (SF0). The following
interface formats can be selected (see also Table 4):
I2S-bus with data word length of up to 24 bits
LSB-justified format with data word length of
16, 20 or 24 bits.
Table 4 Input format selection in the static mode
INPUT FORMAT SF1 SF0
I2S-bus
00
LSB-justified 16 bits
01
LSB-justified 20 bits
10
LSB-justified 24 bits
11
8.8 L3 mode
The device is set to L3 mode by setting the STATIC pin to
LOW. The device can then be controlled via the L3
microcontroller interface (see Chapter 9).
8.8.1 DIGITAL INTERFACE FORMATS
The following interface formats can be selected in the
L3 mode:
I2S-bus with data word length of up to 24 bits
MSB-justified with data word length of up to 24 bits
LSB-justified format with data word length of 16, 18,
20 or 24 bits.
8.8.2 L3 ADDRESS
The UDA1328 can be addressed via the L3 microcontroller
interface using one of two addresses. This is done in order
to individually control the UDA1328 and other Philips
DACs or CODECs via the same L3 bus.
The address can be selected using pin 25 (DEEM0) in
L3 mode. When pin 25 is set LOW, the address is 000100.
When pin 25 is set HIGH the address is 000101.
It should be noted that the digital audio interface holds that
the BCK frequency can be 64 times the WS maximum
frequency, or fBCK 64 × fWS
2001 Mar 27
8







UDA1328T equivalent, schematic
Philips Semiconductors
Multi-channel filter DAC
Product specification
UDA1328T
9.3.6 DE-EMPHASIS
A 2-bit value to enable the digital de-emphasis filter.
Table 18 De-emphasis settings
DE2 DE1 DE0
FUNCTION
0 0 0 no de-emphasis
0 0 1 de-emphasis; 32 kHz
0 1 0 de-emphasis; 44.1 kHz
0 1 1 de-emphasis; 48 kHz
1 0 0 de-emphasis; 96 kHz
9.3.7 OUTPUT POLARITY CONTROL
A 1-bit value to program the output polarity of the output
signal. This bit must be used together with the CH2 to CH0
bits and the ACH bit to either select the polarity for all
channels or to set for each channel individually.
Table 19 Output polarity control
PLC
0
1
FUNCTION
non-inverting
inverting
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
VDDD
VDDA
Txtal(max)
Tstg
Tamb
Ves
PARAMETER
digital supply voltage
analog supply voltage
maximum crystal temperature
storage temperature
ambient temperature
electrostatic handling
Ilu(prot)
Isc(DAC)
latch-up protection current
DAC short-circuit current:
output short-circuited to VSSA(DAC)
output short-circuited to VDDA(DAC)
CONDITIONS
note 1
note 1
note 2
note 3
Tamb = 125 °C; VDD = 3.6 V
Tamb = 0 °C; VDD = 3.0 V;
note 4
MIN.
65
40
3 000
250
MAX.
5.0
5.0
150
+125
+85
+3 000
+250
200
UNIT
V
V
°C
°C
°C
V
V
mA
482 mA
346 mA
Notes
1. All supply connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kseries resistor, expect pin 19 (L3DATA) which can
withstand ESD pulses of 2500 to +2500 V.
3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor.
4. DAC operation cannot be guaranteed after a short-circuit has occurred.
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
2001 Mar 27
16










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