DataSheet8.cn


PDF ( 数据手册 , 数据表 ) HCPL-090J

零件编号 HCPL-090J
描述 (HCPL-09xx) High Speed Digital Isolators
制造商 Hewlett-Packard
LOGO Hewlett-Packard LOGO 


1 Page

No Preview Available !

HCPL-090J 数据手册, 描述, 功能
Agilent HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators
Data Sheet
Description
The HCPL-90xx and HCPL-09xx
CMOS digital isolators feature
high speed performance and
excellent transient immunity
specifications. The symmetric
magnetic coupling barrier gives
these devices a typical pulse
width distortion of 2 ns, a typical
propagation delay skew of 4 ns
and 100 Mbaud data rate, making
them the industrys fastest
digital isolators.
The single channel digital isola-
tors (HCPL-9000/-0900) features
an active-low logic output enable.
The dual channel digital isolators
are configured as unidirectional
(HCPL-9030/-0930) and bi-
directional (HCPL-9031/-0931),
operating in full duplex mode
making it ideal for digital
fieldbus applications.
The quad channel digital isola-
tors are configured as unidirec-
tional (HCPL-900J/-090J), two
channels in one direction and
two channels in opposite direc-
tion (HCPL-901J/-091J), and one
channel in one direction and
three channels in opposite
direction (HCPL-902J/-092J).
These high channel density make
them ideally suited to isolating
data conversion devices, parallel
buses and peripheral interfaces.
They are available in 8-pin PDIP,
8-pin Gull Wing, 8-pin SOIC
packages, and 16pin SOIC
narrow-body and wide-body
packages. They are specified over
the temperature range of -40° C
to +100° C.
CAUTION: It is advised that
normal static precautions be
taken in handling and assembly
of this component to prevent
damage and/or degradation,
which may be induced by ESD.
Features
• +3.3V and +5V TTL/CMOS
compatible
• 3 ns max. pulse width distortion
• 6 ns max. propagation delay skew
• 15 ns max. propagation delay
• High speed: 100 MBd
• 15 kV/µs min. common mode
rejection
• Tri-state output
(HCPL-9000/-0900)
• 2500 V RMS isolation
• UL1577 and IEC 61010-1 approved
Applications
• Digital fieldbus isolation
• Multiplexed data transmission
• Computer peripheral interface
• High speed digital systems
• Isolated data interfaces
• Logic level shifting







HCPL-090J pdf, 数据表
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +3.3 V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Quiescent Supply Current 1
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
IDD1
0.008
0.008
1.5
0.016
3.3
1.5
mA VIN = 0V
0.01
0.01
2.0
0.02
4.0
2.0
Quiescent Supply Current 2
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
IDD2
mA VIN = 0V
3.3 4.0
3.3 4.0
1.5 2.0
5.5 8.0
3.3 4.0
3.0 6.0
Logic Input Current
Logic High Output Voltage
Logic Low Output Voltage
Switching Specifications
IIN
VOH
VOL
-10
VDD2 0.1
0.8*VDD2
VDD2
VDD2 0.5
0
0.5
10 µA
V IOUT = -20 µA, VIN= VIH
V IOUT = -4 mA, VIN= VIH
0.1 V IOUT = 20 µA, VIN= VIL
0.8 V IOUT = 4 mA, VIN= VIL
Maximum Data Rate
Clock Frequency
100 110
MBd CL = 15 pF
fmax 50 MHz
Propagation Delay Time to Logic
Low Output
tPHL
12 18 ns
Propagation Delay Time toLogic
High Output
tPLH
12 18 ns
Pulse Width
tPW
Pulse Width Distortion[1]
|tPHL tPLH|
|PWD|
Propagation Delay Skew[2]
tPSK
Output Rise Time (10 90%)
tR
Output Fall Time (10 90%)
tF
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
tPHZ
Low to High Impedance
tPLZ
High Impedance to High
tPZH
High Impedance to Low
tPZL
Channel-to-Channel Skew
(Dual and Quad Channels)
tCSK
10
2
4
2
2
3
3
3
3
2
ns
3 ns
6 ns
4 ns
4 ns
5 ns
5 ns
5 ns
5 ns
3 ns
Common Mode Transient Immunity
(Output Logic High or Logic Low)[3]
|CMH|
|CML|
15
18
kV/µs Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
8














页数 12 页
下载[ HCPL-090J.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
HCPL-0900(HCPL-09xx) High Speed Digital IsolatorsHewlett-Packard
Hewlett-Packard
HCPL-090J(HCPL-09xx) High Speed Digital IsolatorsHewlett-Packard
Hewlett-Packard

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap