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PDF ( 数据手册 , 数据表 ) STP140NF75

零件编号 STP140NF75
描述 N-CHANNEL Power MOSFET
制造商 ST Microelectronics
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STP140NF75 数据手册, 描述, 功能
STB140NF75 STP140NF75
STB140NF75-1
N-CHANNEL 75V - 0.0065 -120A D²PAK/I²PAK/TO-220
STripFET™ II POWER MOSFET
AUTOMOTIVE SPECIFIC
TYPE
VDSS
RDS(on)
ID
STB140NF75
STP140NF75
STB140NF75-1
75 V
75 V
75 V
<0.0075
<0.0075
<0.0075
120 A(**)
120 A(**)
120 A(**)
s TYPICAL RDS(on) = 0.0065
s SURFACE-MOUNTING D²PAK (TO-263)
POWER PACKAGE
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalanche characteristics and
less critical alignment steps therefore a
remarkable manufacturing reproducibility.
APPLICATIONS
s HIGH CURRENT, HIGH SWITCHING SPEED
s SOLENOID AND RELAY DRIVERS
s AUTOMOTIVE 42V BATTERY DRIVERS
3
1
D2PAK
TO-263
(Suffix “T4”)
123
I2PAK
TO-262
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
Ordering Information
SALES TYPE
STB140NF75T4
STP140NF75
STB140NF75-1
MARKING
B140NF75
P140NF75
B140NF75
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS
VDGR
VGS
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 k)
Gate- source Voltage
ID(**)
ID
IDM(•)
Ptot
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
Drain Current (pulsed)
Total Dissipation at TC = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
EAS (2) Single Pulse Avalanche Energy
Tstg Storage Temperature
Tj Operating Junction Temperature
(•) Pulse width limited by safe operating area.
(**) Current Limited by Package
December 2002
PACKAGE
D2PAK
TO-220
I2PAK
PACKAGING
TAPE & REEL
TUBE
TUBE
Value
75
75
± 20
120
100
480
310
2.08
10
750
Unit
V
V
V
A
A
A
W
W/°C
V/ns
mJ
-55 to 175
°C
(1) ISD 120A, di/dt 400A/µs, VDD V(BR)DSS, Tj TJMAX
(2) Starting Tj = 25 oC, ID = 60 A, VDD = 30V
1/14







STP140NF75 pdf, 数据表
STB140NF75 STP140NF75 STB150NF75-1
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 3.1: Switching Time Waveform
Fig. 4: Gate Charge Test Circuit
Fig. 4.1: Gate Charge Test Waveform
8/14














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