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PDF ( 数据手册 , 数据表 ) SY100E155

零件编号 SY100E155
描述 6-BIT 2:1 MUX-LATCH
制造商 Micrel Semiconductor
LOGO Micrel Semiconductor LOGO 


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SY100E155 数据手册, 描述, 功能
6-BIT 2:1
MUX-LATCH
SY10E155
SY100E155
FEATURES
s 750ps max. LEN to output
s Extended 100E VEE range of –4.2V to –5.5V
s 700ps max. D to output
s Single-ended outputs
s Asynchronous Master Reset
s Dual latch-enables
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75Kinput pulldown resistors
s Fully compatible with Motorola MC10E/100E155
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E155 offer six 2:1 multiplexers followed
by latches with single-ended outputs, designed for use in
new, high-performance ECL systems. The two external
latch-enable signals (LEN1 and LEN2) are gated through a
logical OR operation before use as control for the six
latches. When both LEN1 and LEN2 are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN1 or LEN2 (or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL (Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
BLOCK DIAGRAM
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
D5a
D5b
SEL
LEN1
LEN2
MR
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
DQ
E
NR
DQ
E
NR
DQ
E
NR
DQ
E
NR
DQ
E
NR
DQ
E
NR
Q0
Q1
Q2
Q3
Q4
Q5
PIN CONFIGURATION
D5b
LEN1
LEN2
VEE
MR
SEL
D0b
25 24 23 22 21 20 19
26 18
27 17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q5
Q4
VCC
Q3
Q2
VCCO
Q1
PIN NAMES
Pin
D0a–D5a
D0b–D5b
SEL
LEN1, LEN2
MR
Q0–Q5
VCCO
Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
Outputs
VCC to Output
Rev.: C Amendment: /1
1 Issue Date: February, 1998












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