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PDF ( 数据手册 , 数据表 ) ATMEGA1281

零件编号 ATMEGA1281
描述 8-BIT Microcontroller
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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ATMEGA1281 数据手册, 描述, 功能
Atmel ATmega640/V-1280/V-1281/V-2560/V-2561/V
8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash
Features
High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller
Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16MHz
– On-Chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
– 64K/128K/256KBytes of In-System Self-Programmable Flash
– 4Kbytes EEPROM
– 8Kbytes Internal SRAM
– Write/Erase Cycles:10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85C/ 100 years at 25C
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Endurance: Up to 64Kbytes Optional External Memory Space
Atmel® QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
JTAG (IEEE® std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits
(ATmega1281/2561, ATmega640/1280/2560)
– Output Compare Modulator
– 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)
– Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560)
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
I/O and Packages
– 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)
– 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)
– 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)
– RoHS/Fully Green
Temperature Range:
– -40C to 85C Industrial
Ultra-Low Power Consumption
– Active Mode: 1MHz, 1.8V: 500µA
– Power-down Mode: 0.1µA at 1.8V
Speed Grade:
– ATmega640V/ATmega1280V/ATmega1281V:
• 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
– ATmega2560V/ATmega2561V:
• 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
– ATmega640/ATmega1280/ATmega1281:
• 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V
– ATmega2560/ATmega2561:
• 0 - 16MHz @ 4.5V - 5.5V
DATASHEET
2549Q–AVR–02/2014







ATMEGA1281 pdf, 数据表
2.3.6 Port D (PD7..PD0)
2.3.7
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf-
fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 80.
Port E (PE7..PE0)
2.3.8
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buf-
fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 82.
Port F (PF7..PF0)
2.3.9
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal
pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not
running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be
activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
Port G (PG5..PG0)
Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset con-
dition becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 86.
2.3.10 Port H (PH7..PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buf-
fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 88.
2.3.11 Port J (PJ7..PJ0)
Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a
reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special
features of the ATmega640/1280/2560 as listed on page 90.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
8







ATMEGA1281 equivalent, schematic
7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM
Bit
0x3B (0x5B)
Read/Write
Initial Value
7
RAMPZ7
R/W
0
6
RAMPZ6
R/W
0
5
RAMPZ5
R/W
0
4
RAMPZ4
R/W
0
3
RAMPZ3
R/W
0
2
RAMPZ2
R/W
0
1
RAMPZ1
R/W
0
0
RAMPZ0
R/W
0
RAMPZ
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note
that LPM is not affected by the RAMPZ setting.
Figure 7-4. The Z-pointer used by ELPM and SPM
Bit
(Individually)
7
0
RAMPZ
Bit (Z-pointer)
23
16
7
ZH
15
0
8
70
ZL
70
7.6.2
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.
For compatibility with future devices, be sure to write these bits to zero.
EIND – Extended Indirect Register
Bit
0x3C (0x5C)
Read/Write
Initial Value
7
EIND7
R/W
0
6
EIND6
R/W
0
5
EIND5
R/W
0
4
EIND4
R/W
0
3
EIND3
R/W
0
2
EIND2
R/W
0
1
EIND1
R/W
0
0
EIND0
R/W
0
EIND
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and
ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the EIND setting.
Figure 7-5. The Indirect-pointer used by EICALL and EIJMP
Bit
(Individually)
Bit (Indirect-
pointer)
7
EIND
23
0
16
7
ZH
15
0
8
7
ZL
7
0
0
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.
For compatibility with future devices, be sure to write these bits to zero.
7.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 7-6 on page 17 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS
per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per
power-unit.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
16










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