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PDF ( 数据手册 , 数据表 ) ST92195C

零件编号 ST92195C
描述 (ST92195C/D) 48-96 Kbyte ROM HCMOS MCU
制造商 ST Microelectronics
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ST92195C 数据手册, 描述, 功能
ST92195C/D
48-96 Kbyte ROM HCMOS MCU WITH
ON-SCREEN DISPLAY AND TELETEXT DATA SLICER
s Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s 0°C to +70°C operating temperature range
s Up to 24 MHz. operation @ 5V±10%
s Min. instruction cycle time: 165ns at 24 MHz.
s 48, 56, 64, 84 or 96 Kbytes ROM
s 256 bytes RAM of Register file (accumulators or
index registers)
s 256 to 512 bytes of on-chip static RAM
s 2 or 8 Kbytes of TDSRAM (Teletext and Display
Storage RAM)
s 28 fully programmable I/O pins
s Serial Peripheral Interface
s Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
s Enhanced display controller with 26 rows of
40/80 characters
– 2 sets of 512 characters
– Serial and Parallel attributes
– 10x10 dot matrix, definable by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes
s Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
s VPS and Wide Screen Signalling slicer
s Integrated Sync Extractor and Sync Controller
s 14-bit Voltage Synthesis for tuning reference
voltage
s Up to 6 external interrupts plus one Non-
Maskable Interrupt
s 8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
s 16-bit watchdog timer with 8-bit prescaler
s 1 or 2 16-bit standard timer(s) with 8-bit
prescaler
PSDIP56
TQFP64
See end of Datasheet for ordering information
s I²C Master/Slave (on some devices)
s 4-channel A/D converter; 5-bit guaranteed
s Rich instruction set and 14 addressing modes
s Versatile development tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
s Pin-compatible EPROM and OTP devices
available
Device Summary
Device ROM RAM TDSRAM I²C Timer
ST92195C3
256 2K
ST92195C4 48K
6K
ST92195C5
ST92195C6 56K
No 1
512
ST92195C7 64K
8K
ST92195C8 84K
ST92195C9 96K
ST92195D5 48K
ST92195D6 56K 512
8K Yes 2
ST92195D7 64K
October 2003
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ST92195C pdf, 数据表
ST92195C/D - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92195C and ST92195D microcontrollers
are developed and manufactured by STMicroelec-
tronics using a proprietary n-well HCMOS proc-
ess. Their performance derives from the use of a
flexible 256-register programming model for ultra-
fast context switching and real-time event re-
sponse. The intelligent on-chip peripherals offload
the ST9 core from I/O and data management
processing tasks allowing critical application tasks
to get the maximum use of core resources. The
ST92195C/D MCU support low power consump-
tion and low voltage operation for power-efficient
and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which in-
cludes the control and status registers of the on-
chip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripherals
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete sys-
tem for TV set and VCR applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM of two 512-char-
acter sets. The character resolution is 10x10 dot.
Four character sizes are supported. Serial at-
tributes allow the user to select foreground and
background colors, character size and fringe back-
ground. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
1.1.6 Teletext and Display Storage RAM
The internal Teletext and Display storage RAM
can be used to store Teletext pages as well as Dis-
play parameters.
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ST92195C equivalent, schematic
ST92195C/D - GENERAL DESCRIPTION
Port
Name
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
General
Purpose I/O
All ports useable
for general pur-
pose I/O (input,
output or bidi-
rectional)
Pin No.
TQFP64 SDIP56
44 46
45 47
46 48
47 49
14 20
13 19
PWM4
SCL2
PWM5
SDA2
PWM6
EXTRG
PWM7
STOUT0
INT2
SCK
SCL1
SDO
SDI
SDA1
Alternate Functions
O PWM Output 4
I/O I²C Channel 2 Serial Clock 1)
O PWM Output 5
I/O I²C Channel 2 Serial Data 1)
O PWM Output 6
I A/D Converter External Trigger Input
O PWM Output 7
O Standard Timer 0 Output
I External Interrupt 2
O SPI Serial Clock
I/O I²C Channel 1 Serial Clock 1)
O SPI Serial Data Out
I SPI Serial Data In
I/O I²C Channel 1 Serial Data 1)
Note 1: I²C available on ST92195D devices only.
Table 2. I/O Port Styles
Pins
Weak Pull-Up
Port Style
Reset Values
P0[7:0]
no
Standard I/O
BID / OD / TTL
P2[5,4,3,2]
no
Standard I/O
BID / OD / TTL
P2[1,0]
no
Schmitt trigger
BID / OD / TTL
P3.7
yes
Standard I/O
AF / PP / TTL
P3[6,5,4]
no
Standard I/O
BID / OD / TTL
P4[7:0]
no
Standard I/O
BID / OD / TTL
P5[1:0]
no
Standard I/O
BID / OD / TTL
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain
PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table
To configure the I/O ports, use the information in
this table and the Port Bit Configuration Table in
the I/O Ports Chapter on page 71.
– If WPU = yes, then the WPU can be enabled/dis-
able by software
– If WPU = no, then enabling the WPU by software
has no effect
Port Style= the hardware characteristics fixed for
each port line.
Inputs:
– If port style = Standard I/O, either TTL or CMOS
input level can be selected by software.
– If port style = Schmitt trigger, selecting CMOS or
TTL input by software has no effect, the input will
always be Schmitt Trigger.
Weak Pull-Up = This column indicates if a weak
pull-up is present or not.
Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:
An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corre-
sponding peripheral. Exception to this are ADC
analog inputs which must be explicitly selected
as AF by software.
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