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PDF ( 数据手册 , 数据表 ) AD5255

零件编号 AD5255
描述 3-Channel Digital Potentiometer with Nonvolatile Memory
制造商 Analog Devices
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AD5255 数据手册, 描述, 功能
3-Channel Digital Potentiometer with
Nonvolatile Memory
AD5255
FEATURES
3 channels:
Dual 512-position
Single 128-position
25 kΩ or 250 kΩ full-scale resistance
Low temperature coefficient:
Potentiometer divider 15 ppm/°C
Rheostat mode 35 ppm/°C
Nonvolatile memory retains wiper settings
Permanent memory write protection
Linear increment/decrement
±6 dB increment/decrement
I2C-compatible serial interface
2.7 V to 5.5 V single-supply operation
±2.25 V to ±2.75 V dual-supply operation
Power-on reset time
256 bytes general-purpose user EEPROM
11 bytes RDAC user EEPROM
GBIC and SFP compliant EEPROM
100-year typical data retention at TA = 55°C
APPLICATIONS
Mechanical potentiometer replacement
RGB LED backlight control
White LED brightness adjustment
Programmable gain and offset control
Programmable filters
GENERAL DESCRIPTION
The AD5255 provides dual 512-position and a single
128-position digitally controlled variable resistors1 (VR) in a
TSSOP package. This device performs the same electronic
adjustment function as a potentiometer, trimmer, or variable
resistor. Each VR offers a completely programmable value of
resistance between the A terminal and the wiper or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
25 kΩ or 250 kΩ has a 1% channel-to-channel matching
tolerance and a nominal temperature coefficient of 35 ppm/°C.
Wiper position programming, EEPROM2 reading, and EEPROM
writing is conducted via the standard 2-wire I2C interface. Pre-
vious/default wiper position settings can be stored in memory,
and refreshed upon system power-up.
FUNCTIONAL BLOCK DIAGRAM
VDD
VSS
GND
SCL
SDA
A0_RDAC
A1_RDAC
A0_E
A1_E
RS
WP
I2C
SERIAL
INTERFACE
POWER-ON
RESET
256 BYTES
USER
EEPROM
32 BYTES
RDAC
EEPROM
DATA
CONTROL
COMMAND
DECODE
LOGIC
ADDRESS
DECODE
LOGIC
DECODE
LOGIC
RDAC0
9 BIT
RDAC1
9 BIT
RDAC2
7 BIT
A0
W0
B0
A1
W1
B1
A2
W2
B2
Figure 1.
Additional features of the AD5255 include preprogrammed
linear and logarithmic increment/decrement wiper changing.
The actual resistor tolerances are stored in EEPROM so that the
actual end-to-end resistance is known, which is valuable for
calibration in precision applications.
The AD5255 is available in a 24-lead TSSOP package. All parts
are guaranteed to operate over the extended industrial tempera-
ture range of −40°C to +85°C.
1 The terms programmable resistor, variable resistor, RDAC, and digital
potentiometer are used interchangeably.
2 The terms nonvolatile memory, EEMEM, and EEPROM are used
interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.







AD5255 pdf, 数据表
AD5255
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
TA = –40°C, 25°C, 85°C SUPERIMPOSED
0.8 VDD = 5V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
64 128 192 256 320 384 448 512
CODE (DECIMAL)
Figure 4. INL—9-Bit RDAC
1.50
1.25
1.00
TA = –40°C, 25°C, 85°C SUPERIMPOSED
VDD = 5V
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
0
64 128 192 256 320 384 448 512
CODE (DECIMAL)
Figure 5. DNL—9-Bit RDAC
1.0
TA = –40°C, 25°C, 85°C SUPERIMPOSED
0.8 VDD = 5V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
64 128 192 256 320 384 448 512
CODE (DECIMAL)
Figure 6. R-INL—9-Bit RDAC
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8 TA = –40°C, 25°C, 85°C SUPERIMPOSED
VDD = 5V
–1.0
0 64 128 192 256 320 384 448 512
CODE (DECIMAL)
Figure 7. R-DNL—9-Bit RDAC
0.5
TA = –40°C, 25°C, 85°C SUPERIMPOSED
0.4 VDD = 5V
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
16 32 48 64 80 96
CODE (DECIMAL)
Figure 8. INL—7-Bit RDAC
112 128
0.5
TA = –40°C, 25°C, 85°C SUPERIMPOSED
0.4 VDD = 5V
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
16 32 48 64 80 96
CODE (DECIMAL)
Figure 9. DNL—7-Bit RDAC
112 128
Rev. 0 | Page 8 of 20







AD5255 equivalent, schematic
AD5255
USING ADDITIONAL INTERNAL
NONVOLATILE EEPROM
The AD5255 contains additional internal user EEPROM for
saving constants and other data. The user EEPROM I2C data
word follows the same format as the general-purpose EEPROM
memory shown in Figure 19 and Figure 20. User EEPROM
memory addresses are shown in Table 6.
To support the use of multiple EEPROM modules on a single
I2C bus, the AD5255 features two external addressing pins, Pins
21 and 22 (A1_EE and A0_EE) to manually set the address of
the EEPROM included with the AD5255. This feature ensures
that the correct EEPROM memory is accessed when using
multiple memory modules on a single I2C bus.
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD protected. Digital inputs are high
impedance and can be driven directly from most digital sources.
The RESET digital input pin does not have an internal pull-up
resistor. Therefore, the user should place a pull-up resistor from
RESET to VDD if the function is not used. The WP pin has an
internal pull-down resistor. If not driven by an external source,
the AD5255 defaults to a write-protected state. ESD protection
of the digital inputs is shown in Figure 27.
VDD
INPUTS
WP
GND
Figure 27. Equivalent WP ESD Protection
MULTIPLE DEVICES ON ONE BUS
Figure 28 shows four AD5255 devices on the same serial bus.
Each has a different slave address since the state of their AD0
and AD1 pins are different. This allows independent reading
and writing to each RDAC within each device.
+5V
RP RP
MASTER
SDA
SCL
VDD
VDD
VDD
SDA SCL
SDA SCL
SDA SCL
SDA SCL
AD1
AD1
AD1
AD1
AD0
AD0
AD0
AD0
Figure 28. Multiple AD5255 Devices on a Single Bus
LEVEL SHIFT FOR BIDIRECTIONAL
COMMUNICATION
While most legacy systems operate at one voltage, adding a new
component might require a different voltage. When two systems
transmit the same signal at two different voltages, use a level
shifter to allow the systems to communicate.
For example, a 3.3 V microcontroller (MCU) can be used along
with a 5 V digital potentiometer. A level shifter is required to
enable bidirectional communication.
Figure 29 shows one of many possible techniques to properly
level-shift signals between two devices. M1 and M2 are
N-channel FETs (2N7002). If VDD falls below 2.5 V, use low
threshold N-channel FETs (FDV301N) for M1 and M2.
VDD1 = 3.3V
VDD2 = 5V
SDA1
SCL1
RP RP
RP RP
G
SD
G
M1 S
D
M2
SDA2
SCL2
3.3V
MCU
5V
AD5255
Figure 29. Level Shifting for Different Voltage Devices on an I2C Bus
TERMINAL VOLTAGE OPERATION RANGE
The AD5255 positive VDD and negative VSS power supply inputs
define the boundary conditions for proper 2-terminal
programmable resistance operation. Supply signals on terminals
W and B that exceed VDD or VSS are clamped by the internal
forward-biased diodes of the AD5255.
VDD
A
W
B
VSS
Figure 30. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5255 is used as a digital ground
reference, and needs to be tied to the common ground of the
PCB. Reference the digital input control signals to the AD5255
ground pin, and satisfy the logic levels defined in the
Specifications tables.
Rev. 0 | Page 16 of 20










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