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PDF ( 数据手册 , 数据表 ) ID82C84A

零件编号 ID82C84A
描述 CMOS Clock Generator Driver
制造商 Intersil Corporation
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ID82C84A 数据手册, 描述, 功能
82C84A
March 1997
CMOS Clock Generator Driver
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C84A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C84A is a high performance CMOS Clock Generator-
driver which is designed to service the requirements of both CMOS
and NMOS microprocessors such as the 80C86, 80C88, 8086 and
the 8088. The chip contains a crystal controlled oscillator, a divide-by-
three counter and complete “Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external fre-
quency source from DC to 25MHz. Crystal controlled operation to
25MHz is guaranteed with the use of a parallel, fundamental mode
crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over tempera-
ture and voltage ranges.
Power consumption is a fraction of that of the equivalent bipolar cir-
cuits. This speed-power characteristic of CMOS permits the
designer to custom tailor his system design with respect to power
and/or speed requirements.
Ordering Information
PART
NUMBER
CP82C84A
IP82C84A
CS82C84A
IS82C84A
CD82C84A
ID82C84A
MD82C84A/B
8406801VA
MR82C84A/B
84068012A
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE
PKG.
NO.
18 Ld PDIP E18.3
E18.3
20 Ld PLCC N20.35
N20.35
18 Ld CERDIP F18.3
F18.3
F18.3
SMD#
F18.3
20 Pad CLCC J20.A
SMD#
J20.A
Pinouts
82C84A (PDIP, CERDIP)
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
18 VCC
17 X1
16 X2
15 ASYNC
14 EFI
13 F/C
12 OSC
11 RES
10 RESET
82C84A (PLCC, CLCC)
TOP VIEW
3 2 1 20 19
RDY1 4
READY 5
RDY2 6
AEN2 7
NC 8
18 X2
17 ASYNC
16 EFI
15 F/C
14 NC
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-287
File Number 2974.1







ID82C84A pdf, 数据表
82C84A
Test Load Circuits
OUTPUT FROM
DEVICE UNDER TEST
2.25V
R = 740FOR ALL OUTPUTS
EXCEPT CLK
463FOR CLK OUTPUT
CL
(SEE NOTE 3)
NOTES:
1. CL =100pF for CLK output.
2. CL = 50pF for all outputs except CLK.
3. CL = Includes probe and jig capacitance.
FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS
X1 CLK
LOAD
PULSE
EF1 CLK
LOAD
(SEE NOTE 1)
GENERATOR
(SEE NOTE 1)
C1
X2 VCC
C2 F/C
F/C
CSYNC
CSYNC
FIGURE 6. TCHCL, TCLCH LOAD CIRCUITS
24MHz
PULSE
GENERATOR
TRIGGER
VCC
C1
C2
AEN1 CLK
X1
READY
X2
RDY2 OSC
F/C
AEN2
CSYNC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
PULSE
GENERATOR
TRIGGER
PULSE
GENERATOR
VCC
EF1 CLK
F/C
AEN1
RDY2 READY
AEN2
CSYNC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
FIGURE 7. TRYLCL, TRYHCH LOAD CIRCUITS
AC Testing Input, Output Waveform
INPUT
VIH + 0.4V
OUTPUT
VOH
1.5V
1.5V
VIL - 0.4V
VOL
NOTE: Input test signals must switch between VIL (maximum) -0.4V and VIH (minimum) +0.4V. RES and F/C must switch between 0.4V and
VCC -0.4V. Input rise and fall times driven at 1ns/V. VIL VIL (max) -0.4V for CSYNC pin. VCC -4.5V and 5.5V.
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