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PDF ( 数据手册 , 数据表 ) UDA1334ATS

零件编号 UDA1334ATS
描述 Low power audio DAC with PLL
制造商 NXP Semiconductors
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UDA1334ATS 数据手册, 描述, 功能
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DATA SHEET
UDA1334ATS
Low power audio DAC with PLL
Product specification
Supersedes data of 2000 Feb 09
File under Integrated Circuits, IC01
2000 Jul 31







UDA1334ATS pdf, 数据表
Philips Semiconductors
Low power audio DAC with PLL
Product specification
UDA1334ATS
8.4 Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. No post filter is needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally to
the power supply voltage.
8.5 Power-on reset
The UDA1334ATS has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1 µs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) < 0.75 V.
During the reset time the system clock should be running.
handbook, halfpage
3.0 V
VDDA
13
Vref(DAC) 12
50 k
RESET
CIRCUIT
C1 >
10 µF
50 k
UDA1334ATS
MGT015
Fig.3 Power-on reset circuit.
3.0
handVbDooDk,Dhalfpage
(V)
1.5
0
3.0
VDDA
(V)
1.5
t
0
3.0
Vref(DAC)
(V)
1.5
1.25
0.75
0
>1 µs
Fig.4 Power-on reset timing.
t
t
MGL984
2000 Jul 31
8







UDA1334ATS equivalent, schematic
Philips Semiconductors
Low power audio DAC with PLL
Product specification
UDA1334ATS
analog
supply voltage
digital
supply voltage
R7
C9 1
R6
C5 1
47 µF
(16 V)
C10
47 µF
(16 V)
C6
27 MHz
clock
MPEG
DECODER
R5 SYSCLK/PLL1 6
47
I2S-bus
(master)
BCK 1
WS 2
DATAI 3
SFOR1 7
SFOR0 11
100 nF
(63 V)
VSSA VDDA
15 13
100 nF
(63 V)
VSSD VDDD
54
VOUTL C3
14
47 µF
(16 V)
UDA1334ATS
VOUTR C4
16
47 µF
(16 V)
R3
100
R1
220 kC1
R4
100
R2
220 kC2
MUTE 8
DEEM/CLKOUT
9
audio clock PLL0 10
Vref(DAC)
12
C8
100 nF
(63 V)
C7
47 µF
(16 V)
left
output
10 nF
(63 V)
right
output
10 nF
(63 V)
MGL974
In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is
slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock.
Fig.9 Video mode application diagram.
2000 Jul 31
16










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