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PDF ( 数据手册 , 数据表 ) I.MX31L

零件编号 I.MX31L
描述 Multimedia Applications Processors
制造商 Freescale Semiconductor
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I.MX31L 数据手册, 描述, 功能
Freescale Semiconductor
Product Brief
Document Number: MC1128MX31PB
Rev. 0.6, 06/2005
i.MX31 and i.MX31L
Multimedia Applications Processors
1 Introduction
The i.MX31 and i.MX31L multimedia applications
processors represent Freescale Semiconductor’s latest
achievement in multimedia integrated applications
processors that are part of a growing family of
multimedia-focused products offering high performance
processing optimized for lowest power consumption.
The i.MX31 and i.MX31L processors feature Freescale's
advanced and power-efficient implementation of the
ARM1136JF-S™ core, which operates at speeds starting
at 532 MHz.
Unless otherwise specified, the material in this product
brief is applicable to both the i.MX31 and i.MX31L
processors. Features include the following:
Smart Speed Technology—The heart of the
i.MX31 and i.MX31L processors is a level of
power management throughout the ICs that allow
the rich suite of multimedia features and
peripherals to achieve minimum system power
consumption in both active and various
low-power modes. Smart Speed Technology
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
© Freescale Semiconductor, Inc., 2005. All rights reserved.







I.MX31L pdf, 数据表
Features
ARM® Processing
• Huffman decoding, run-
length decoding and inverse
scan
• Inverse quantization, IDCT &
motion compensation
Camera
IPU Processing
De-blocking, de-ringing,
resizing, color conversion,
combining with graphics
Display
i.MX31/i.MX31L EMI
ARM11TM CPU
IPU
MPEG-4 Encoder
Memory
MPEG-4 Stream
Reference
Frame Buffer
Video Input
Double Buffer
Graphics
Overlay
Display
Double Buffer
Figure 5. MPEG4 SP Video Play-Back—Data Flow
2.5 2D/3D Graphics Support
The i.MX31 processor includes the Graphics Processing Unit (GPU) to provide hardware acceleration for
2D and 3D graphics algorithms. The acceleration is enough to run desktop quality interactive graphics
applications on displays with the screen resolution of VGA and above and color representation up to 32
bits per pixel. The GPU uses the ARM MBX R-S graphics accelerator. Figure 6 on page 9 shows the GPU
high level block diagram and processing data flow.
NOTE
The Graphics Processing Unit (GPU) is not available in the i.MX31L
processor.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
8 Freescale Semiconductor







I.MX31L equivalent, schematic
Features
Subscriber Identification Module (SIM)—The Subscriber Identification Module interfaces to an
external Subscriber Identification Card. It is an asynchronous serial interface adapted for Smart
Card communication for e-Commerce applications. The module is compliant with the ISO 7816-3
standard.
Multimedia Card/Secure Digital Host (MMC/SD)—Each i.MX31 and i.MX31L processor
implements two MMC/SD slots. The MMC communication is based on an advanced 7-pin serial
bus designed to operate in a low-voltage range.
The Multimedia Card/Secure Digital Host module (MMC/SD) integrates both MMC support along
with SD memory and I/O functions. In addition to Multimedia and Secure Digital Cards, the
module can be used to communicate to high-bit rate communication devices, such as WLAN
802.11 a/b, Bluetooth wireless technology, and so on.
Memory Stick®/Memory Stick Pro® (MS)—Each i.MX31 and i.MX31L processors’ Memory
Stick module is a host controller that supports two Memory Stick slots. The MS conforms to
Memory Stick Standard Format Specifications, ver.1.4-00 and Memory Stick Standard Memory
Stick PRO Format Specification, ver.1.00-01.
ATA Controller—The ATA block of each i.MX31 and i.MX31L processor is an AT attachment
host interface and used to interface with IDE hard disk drives and ATAPI optical disk drives. This
feature allows designers to attach storage devices at low costs per unit, which is a critical selling
point in the portable digital player market. The ATA controller interfaces with ATA devices using
the industry standard ATA-6 specification.
2.13 System Control
To ensure optimum power use and clock signal stability, the i.MX31 and i.MX31L processors use the
following modules to generate, control, and distribute clock and control signals throughout the i.MX31
and i.MX31L processors and to external devices:
Clock Control Module (CCM)—Provides clock and reset control for each i.MX31 and i.MX31L
processor.
Digital PLL—Produces a high-frequency clock signal with a low frequency and phase jitter. The
DPLL reference is an external system clock frequency (15 MHz–30 MHz).
Frequency Pre-Multiplier (FPM)—Provides clock generation from a reference clock of a low
frequency, for example, a 32 KHz reference clock. The FPM multiplies the reference frequency by
a large factor of 640–15360 and produces a high frequency chip clock with a low-frequency jitter.
This clock may be used as input to DPLL.
I/O Mux Controller (IOMUXC)—Controls the input and output paths of the I/O Mux, pad
properties—for example, pull up/down, hysteresis, and other examples—and interrupt observation.
2.14 Debug
The i.MX31 and i.MX31L processors’ debug features are the enablers for hardware and software debug
and validation of the silicon, either on an evaluation board, a customer’s application board, a closed or
opened radio, PDA, or other device. Debugging is used to identify and isolate the cause of failure when
running hardware against software in a real-time application.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
16 Freescale Semiconductor










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I.MX31LMultimedia Applications ProcessorsFreescale Semiconductor
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