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PDF ( 数据手册 , 数据表 ) 5962-90899

零件编号 5962-90899
描述 EEPROM / NOR FLASH / 128K X 8
制造商 Austin Semiconductor
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5962-90899 数据手册, 描述, 功能
LTR
REVISIONS
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A Updated boilerplate. Added device types 09 - 13. Moved endurance
94-03-25
and data retention testing requirements from Section 4 of drawing to
Section 3 of drawing. Editorial changes throughout.
B Updated boilerplate. Added vendor CAGE 01295 as a source of
supply. Editorial changes throughout. - glg
98-04-16
C Changed standoff width on "U" package. Added vendor CAGE
0EU86 as a source of supply. - glg
99-11-16
M. A. Frye
Raymond Monnin
Raymond Monnin
REV
SHEET
REV
CCCCCCCCCC
SHEET
15 16 17 18 19 20 21 22 23 24
REV STATUS
OF SHEETS
REV
SHEET
CCCCCCCCCCCCC C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
PREPARED BY
Gary L. Gross
CHECKED BY
Ray Monnin
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
92-08-31
AMSC N/A
REVISION LEVEL
C
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
MICROCIRCUIT, MEMORY, DIGITAL, CMOS
128K X 8 BIT FLASH EEPROM, MONOLITHIC SILICON
SIZE
A
CAGE CODE
67268
SHEET
1
OF
5962-90899
24
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E050-00







5962-90899 pdf, 数据表
Test
CAPACITANCE 2/
Input capacitance
TABLE I. Electrical performance characteristics - Continued.
Symbol
Conditions
u-n5l5e4s.5Cs VothTeCVrCwiCs+e12s5p5.e5CcVifi1e/d
Group A
Subgroups
Device
type
Limits
Min Max
CIN1
Vf =IN1=.00MVh,zT, Ase=e
25C,
4.4.1c
4
All
10
Units
pF
Output capacitance
COUT VOUT = 0 V, TA = 25C,
f = 1.0 Mhz, see 4.4.1c
4
All
VPP input capacitance CIN2 VIN = 0 V, TA = 25C,
4 All
f = 1.0 Mhz, see 4.4.1c
AC CHARACTERISTICS - READ ONLY OPERATIONS (See figure 5 as applicable.)
Read cycle time
tAVAV 2/
9, 10, 11
01,05,10
02,06,11
03,07,12
04,08,13
09
250
200
150
120
90
12
12
pF
pF
ns
Chip enable access
time
tELQV
Address access
time
tAVQV
9, 10, 11
01,05,10
02,06,11
03,07,12
04,08,13
09
9, 10, 11
01,05,10
02,06,11
03,07,12
04,08,13
09
250 ns
200
150
120
90
250 ns
200
150
120
90
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
C
5962-90899
SHEET
8







5962-90899 equivalent, schematic
Command definitions, device types 01-09
Command
Read memory
Read auto select codes 4/
Setup erase/erase
Erase verify
Setup program/program
Program verify
Reset 5/
BUS
cycles
required
1
2
2
2
2
2
2
First BUS cycle
Second BUS cycle
Operation
1/
Write
Write
Write
Write
Write
Write
Write
Address Data
2/ 3/
X 00H/FFH
X 90H/80H
X 20H
EA A0H
X 40H
X C0H
X FFH
Operation
1/
Read
Read
Write
Read
Write
Read
Write
Address
2/
RA
IA
X
X
PA
X
X
Data
3/
RD
ID
20H
EVD
PD
PVD
FFH
1/ Refer to BUS operations for definitions.
2/ RA = Address of the memory location to be read.
IA = Identifier address: 00H/01H for manufacturer code, 01H/A7H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Address are latched on the falling edge of the write-enable pulse.
3/ RD = Data read from location RA during read operation.
ID = Data read from location IA during device identification.
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write-enable.
PVD = Data read from location PA during program verify. PA is latched on the program command.
4/ Following the read Auto Select code ID command, two read operations access manufacturer and device codes.
5/ The second bus cycle must be followed by the desired command register write.
Command definitions, device types 10-13
Command
Read memory
Read auto select codes 4/
Embedded erase setup/erase
Embedded program
setup/program
Reset 5/
BUS
cycles
required
1
3
2
2
First BUS cycle
Operation
1/
Write
Write
Write
Write
Address
2/
X
X
X
X
Data
3/
00H/FFH
80H/90H
30H
10H/50H
Second BUS cycle
Operation Address Data
1/ 2/ 3/
Read RA RD
Read 00H/01H 01H/A2H
Write X 30H
Write PA PD
2
Write
X
FFH Write X FFH
1/ Refer to BUS operations for definitions.
2/ RA = Address of the memory location to be read.
PA = Address of memory location to be programmed.
Address are latched on the falling edge of the W E pulse.
3/ RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of W E .
4/ Following the read Auto Select code ID command, two read operations access manufacturer and device codes.
5/ The second bus cycle must be followed by the desired command register write.
FIGURE 3. Truth tables - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
C
5962-90899
SHEET
16










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