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PDF ( 数据手册 , 数据表 ) T85C5121

零件编号 T85C5121
描述 8-bit Microcontroller with Multi protocol SMART Card Interface
制造商 ATMEL Corporation
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T85C5121 数据手册, 描述, 功能
Features
80C51 Core
– 12 or 6 Clocks per Instruction (X1 and X2 Modes)
– 256 Bytes Scratchpad RAM
– Dual Data Pointer
– Two 16-bit Timer/Counters: T0 and T1
T83C5121 with 16 Kbytes Mask ROM
T85C5121 with 16 Kbytes Code RAM
T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM
On-chip Expanded RAM (XRAM): 256 Bytes
Versatile Host Serial Interface
– Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG):
Most Standard Speeds up to 230K bits/s at 7.36 MHz
– Output Enable Input
– Multiple Logic Level Shifters Options (1.8V to VCC)
– Automatic Level Shifter Option
Multi-protocol Smart Card Interface
– Certified with Dedicated Firmware According to ISO 7816, EMV2000, GIE-CB, GSM
11.12V and WHQL Standards
– Asynchronous Protocols T = 0 and T = 1 with Direct and Inverse Modes
– Baud Rate Generator Supporting All ISO7816 Speeds up to D = 32/F = 372
– Parity Error Detection and Indication
– Automatic Character Repetition on Parity Errors
– Programmable Timeout Detection
– Card Clock Stop High or Low for Card Power-down Mode
– Support Synchronous Card with C4 and C8 Programmable Outputs
– Card Detection and Automatic De-activation Sequence
– Step-up/down Converter with Programmable Voltage Output: 5V, 3V (± 8% at
60 mA) and 1.8V (±8% at 20 mA)
– Direct Connection to Smart Card Terminals:
Short Circuit Current Limitation
www.DataSheet4U.com
Logic Level Shifters
4 kV ESD Protection (MIL/STD 833 Class 3)
Alternate Card Support with CLK, I/O and RST According to GSM 11.12V Standard
2x I/O Ports: 6 I/O Port1 and 8 I/O Port3
2x LED Outputs with Programmable Current Sources: 2, 4, or 10 mA
Hardware Watchdog
Reset Output Includes
– Hardware Watchdog Reset
– Power-on Reset (POR)
– Power-fail Detector (PFD)
4-level Priority Interrupt System with 7 Sources
7.36 to 16 MHz On-chip Oscillator with Clock Prescaler
Absolute CPU Maximal Frequency: 16 MHz in X1 mode, 8MHz in X2 mode
Idle and Power-down Modes
Voltage Operation: 2.85V to 5.4V
Low Power Consumption
– 8 mA Operating Current (at 5.4V and 3.68 MHz)
– 150 mA Maximum Current with Smart Card Power-on (at 16 MHz X1 Mode)
– 30 μA Maximum Power-down Current at 3.0V (without Smart Card)
– 100 μA Maximum Power-down Current at 5.4V (without Smart Card)
Temperature Range
– Commercial: 0 to +70°C Operating Temperature
– Industrial: -40 to +85°C Operating Temperature
Packages
– SSOP24
– QFN32
– PLCC52
8-bit
Microcontroller
with Multi-
protocol Smart
Card Interface
T83C5121
T85C5121
T89C5121
AT83C5121
AT85C5121
AT89C5121
Rev. 4164G–SCR–07/06







T85C5121 pdf, 数据表
Table 1. Ports Description (Continued)
Port
Signal
Name
Alternate
Internal
Power
Supply
RST
VCC
XTAL1
XTAL2
VCC
LI
CVCC
DVCC
EVCC
CVSS
VSS
VCC
VCC
VCC
ESD
Type Description
I/O Reset input
Holding this pin low for 64 oscillator periods while the oscillator
is running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than VIL is applied, whether or
not the oscillator is running.
This pin has an internal pull-up resistor which allows the device to be reset by
connecting a capacitor between this pin and VSS.This capacitor is optional
thanks to the internal POR which output a Reset as long as Vcc has not
reached the POR threshold level
Asserting RST when the chip is in Idle mode or Power-down mode
returns the chip to normal operation.
The output is active for at least 12 oscillator periods when an internal
reset occurs.
I Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected
to this pin.
If an external oscillator is used, its output is connected to this pin.
O Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected
to this pin.
If an external oscillator is used, XTAL2 may be left unconnected.
PWR Supply voltage
VCC is used to power the internal voltage regulators and internal I/O’s.
PWR
DC/DC input
LI must be tied to VCC through an external coil (typically 4, 7 μH) and provide
the current for the pump charge of the DC/DC converter.
PWR
Card Supply voltage
CVCC is the programmable voltage output for the Card interface.
It must be connected to an external decoupling capacitor.
PWR
Digital Supply voltage
DVCC is used to supply the digital core and internal I/Os. It is
internally connected to the output of a 3V regulator and must be connected to
an external decoupling capacitor.
PWR
Extra supply voltage
EVCC is used to supply the level shifters of UART interface I/O
pins. It must be connected to an external decoupling capacitor.
This reference voltage is generated internally (automatically or not),
or it can be connected to an external voltage reference.
GND DC/DC ground
CVSS is used to sink high shunt currents from the external coil.
GND Ground
8 A/T8xC5121
4164G–SCR–07/06







T85C5121 equivalent, schematic
Power Monitoring
and Clock
Management
For applications where power consumption is a critical factor, three power modes are
provided:
• Idle mode
• Power-down mode
• Clock Management (X2 feature and Clock Prescaler)
• 3V Regulator Modes (pulsed or not pulsed)
Idle Mode
An instruction that sets PCON.0 causes the last instruction to be executed before going
into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but
not to the interrupt, Timer 0, and Serial Port functions. The CPU status is preserved in
its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator
and all other registers maintain their data during Idle. The port pins hold the logical
states they had at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-
viced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bit GF0 can be used to give an indication if an interrupt occurred during normal
operation or during an Idle. For example, an instruction that activates Idle can also set
one or both flag bits. When Idle is terminated by an interrupt, the interrupt service rou-
tine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
Entering Power-down Mode
To save maximum power, a Power-down mode can be invoked by software (refer to
Table 3, PCON register).
In Power-down mode, the oscillator is stopped and the instruction that invoked Power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from Power-
down. To properly terminate Power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from Power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 10. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and Power-Down exit will be completed when the
first input will be released. In this case the higher priority interrupt service routine is
executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put it into Power-down mode.
Exit from Power-down Mode Exiting from Power-down by external interrupt does not affect the SFRs and the internal
RAM content.
16 A/T8xC5121
4164G–SCR–07/06










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