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PDF ( 数据手册 , 数据表 ) T89C51AC2

零件编号 T89C51AC2
描述 Enhanced 8-bit Microcontroller
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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T89C51AC2 数据手册, 描述, 功能
Features
80C51 Core Architecture
256 Bytes of On-chip RAM
1 KB of On-chip XRAM
32 KB of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
Read/Write Cycle: 10K
2 KB of On-chip Flash for Bootloader
2 KB of On-chip EEPROM
Read/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
Five Ports: 32 + 2 Digital I/O Lines
Five-channel 16-bit PCA with:
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
Double Data Pointer
21-bit Watchdog Timer (7 Programmable Bits)
10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
On-chip Emulation Logic (Enhanced Hook System)
Power Saving Modes:
– Idle Mode
– Power-down Mode
Power Supply: 3V to 5.5V
Temperature Range: Industrial (-40° to +85°C)
Packages: VQFP44, PLCC44
Description
The A/T89C51AC2 is a high performance Flash version of the 80C51 single chip 8-bit
microcontrollers. It contains a 32 KB Flash memory block for program and data.
The 32 KB Flash memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard VCC pin.
The A/T89C51AC2 retains all features of the 80C51 with 256 bytes of internal RAM, a
7-source 4-level interrupt controller and three timer/counters. In addition, the
A/T89C51AC2 has a 10-bit A/D converter, a 2 KB Boot Flash memory, 2 KB EEPROM
for data, a Programmable Counter Array, an XRAM of 1024 bytes, a Hardware Watch-
Dog Timer, and a more versatile serial channel that facilitates multiprocessor
communication (EUART). The fully static design of the A/T89C51AC2 reduces system
power consumption by bringing the clock frequency down to any value, even DC,
without loss of data.
The A/T89C51AC2 has two software-selectable modes of reduced activity and an 8-
bit clock prescaler for further reduction in power consumption. In the idle mode the
CPU is frozen while the peripherals and the interrupt system are still operating. In the
Power-down mode the RAM is saved and all other functions are inoperative.
The added features of the A/T89C51AC2 make it more powerful for applications that
need A/D conversion, pulse width modulation, high speed I/O and counting capabili-
ties such as industrial control, consumer goods, alarms, motor control, among others.
While remaining fully compatible with the 80C52, the T8C51AC2 offers a superset of
this standard microcontroller. In X2 mode, a maximum external clock rate of 20 MHz
reaches a 300 ns cycle time.
Enhanced 8-bit
Microcontroller
with 32 KB Flash
Memory
AT89C51AC2
T89C51AC2
Rev. 4127H–8051–02/08
1







T89C51AC2 pdf, 数据表
Table 2. Read-Modify-Write Instructions
Instruction
Description
Example
ANL
logical AND
ANL P1, A
ORL
logical OR
ORL P2, A
XRL
logical EX-OR
XRL P3, A
JBC jump if bit = 1 and clear bit
JBC P1.1, LABEL
CPL
complement bit
CPL P3.0
INC
DEC
increment
decrement
INC P2
DEC P2
DJNZ
decrement and jump if not zero
DJNZ P3, LABEL
MOV Px.y, C move carry bit to bit y of Port x
MOV P1.5, C
CLR Px.y
clear bit y of Port x
CLR P2.4
SET Px.y
set bit y of Port x
SET P3.3
It is not obvious the last three instructions in this list are Read-Modify-Write instructions.
These instructions read the port (all 8 bits), modify the specifically addressed bit and
write the new byte back to the latch. These Read-Modify-Write instructions are directed
to the latch rather than the pin in order to avoid possible misinterpretation of voltage
(and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of
an external bipolar transistor can not rise above the transistor’s base-emitter junction
voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU
to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather
than the pins returns the correct logic-one value.
Quasi-Bidirectional Port
Operation
Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as
"quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as
logic one and sources current in response to an external logic zero condition. Port 0 is a
"true bidirectional" pin. The pins float when configured as input. Resets write logic one to
all Port latches. If logical zero is subsequently written to a Port latch, it can be returned
to input conditions by a logical one written to the latch.
Note:
Port latch values change near the end of Read-Modify-Write instruction cycles. Output
buffers (and therefore the pin state) update early in the instruction after Read-Modify-
Write instruction cycle.
Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-
up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This
extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock
periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-
ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses
logical zero and off when the gate senses logical one. pFET #1 is turned on for two
oscillator periods immediately after a zero-to-one transition in the Port latch. A logical
one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter
and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched
on whenever the associated nFET is switched off. This is traditional CMOS switch con-
vention. Current strengths are 1/10 that of pFET #3.
8 A/T89C51AC2
4127H–8051–02/08







T89C51AC2 equivalent, schematic
Figure 6. Mode Switching Waveforms
XTAL1
XTAL1/2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
Note:
In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the
clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running
timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have
a 9600 baud rate.
16 A/T89C51AC2
4127H–8051–02/08










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