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PDF ( 数据手册 , 数据表 ) T89C51RC2

零件编号 T89C51RC2
描述 (T89C51RB2/RC2) 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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T89C51RC2 数据手册, 描述, 功能
Features
80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit timer/counters
– 256 Bytes Scratch Pad RAM
– 10 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
Variable Length MOVX for slow RAM/Peripherals
ISP (In-System Programming) using Standard VCC Power Supply
Boot ROM Contains Low Level FLASH Programming Routines and a Default Serial
Loader
High-Speed Architecture
– 40 MHz in Standard Mode
– 20 MHz in X2 Mode (6 clocks/machine cycle)
16K/32K Bytes on-chip FLASH Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 10k Write Cycles
On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 bytes)
– 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
Keyboard Interrupt Interface on port P1
SPI Interface (Master / Slave Mode)
8-bit Clock Prescaler
Improved X2 Mode with Independent Selection for CPU and each Peripheral
Programmable Counter Array 5 Channels with:
– High Speed Output
– Compare / Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
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Asynchronous Port Reset
Full Duplex Enhanced UART
Dedicated Baud Rate Generator for UART
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time enabled with Reset-Out)
Power Control Modes:
– Idle Mode
– Power-down mode
– Power-off Flag
Power supply: 4.5 to 5.5V or 2.7 to 3.6V
Temperature ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
Packages: PDIL40, PLCC44, VQFP44
8-bit
Microcontroller
with 16K/
32K byte Flash
T89C51RB2
T89C51RC2
Preliminary
Description
T89C51RB2/RC2 is a high-performance FLASH version of the 80C51 8-bit microcon-
trollers. It contains a 16K or 32K byte Flash memory block for program and data.
The Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated
from the standard VCC pin.
The T89C51RB2/RC2 retains all features of the 80C52 with 256 bytes of internal
RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the T89C51RB2/RC2 has a Programmable Counter Array, an XRAM of
1024 bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface,
Rev. 4105D–8051–10/06
1







T89C51RC2 pdf, 数据表
Table 3. Pin Description for 40 - 44 Pin Packages (Continued)
Mnemonic
PSEN
EA
Pin Number
DIL LCC
29 32
VQFP44 1.4 Type
26 O
31 35
29
I
Name and Function
Program Strobe ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to FFFFH (RD). If
security level 1 is programmed, EA will be internally latched on Reset.
8 T89C51RB2/RC2
4105D–8051–10/06







T89C51RC2 equivalent, schematic
Table 8. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
7654
- - ENBOOT -
3
GF3
2
0
10
- DPS
Bit Bit
Number Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Boot Flash
5 ENBOOT Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 GF3 This bit is a general purpose user flag. *
2 0 Always cleared.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
0 DPS Cleared to select DPTR0.
Set to select DPTR1.
Reset Value: XXXX XX0X0b
Not bit addressable
Note: *Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
16 T89C51RB2/RC2
4105D–8051–10/06










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