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PDF ( 数据手册 , 数据表 ) MTB16N25E

零件编号 MTB16N25E
描述 TMOS POWER FET 16 AMPERES
制造商 Motorola Semiconductors
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MTB16N25E 数据手册, 描述, 功能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB16N25E/D
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS E–FET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a drain–to–source diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add –T4
Suffix to Part Number
G
®
D
S
MTB16N25E
Motorola Preferred Device
TMOS POWER FET
16 AMPERES
250 VOLTS
RDS(on) = 0.25 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS 250 Vdc
VDGR 250 Vdc
VGS
± 20 Vdc
VGSM ± 40 Vpk
Drain Current — Continuous
Drain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 16 Adc
ID 10
IDM 56 Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
PD 125 Watts
1.0 W/°C
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 3.0 mH, RG = 25 )
EAS 384 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.0 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1







MTB16N25E pdf, 数据表
MTB16N25E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇ SOLDER PASTE
ÇÇÇÇ OPENINGS
STENCIL
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 17. Typical Stencil for DPAK and
D2PAK Packages
Figure 17 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and soldering
should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.
8 Motorola TMOS Power MOSFET Transistor Device Data














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