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PDF ( 数据手册 , 数据表 ) 5962-87549012

零件编号 5962-87549012
描述 Microcircuit / Digital / Advanced CMOS / Quad 2 Input NAND Gate / Monolithic Silicon
制造商 National Semiconductor
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5962-87549012 数据手册, 描述, 功能
REVISIONS
LTR DESCRIPTION
A Change AC limits in table I. Add vendor CAGE 18714 to device type 01CX.
Editorial changes throughout.
DATE (YR-MO-DA)
87-11-16
B Changes in accordance with NOR 5962-R100-93.
93-03-23
C Changes in accordance with NOR 5962-R181-93.
93-06-25
D Add vendor CAGE F8859. Add device Class V criteria. Add delta limits, table III.
Add case outline X. Update boilerplate to MIL-PRF-38535 requirements. – lgt
01-03-23
E Add section 1.5, radiation features. Update the boilerplate to include radiation
hardness assured requirements. Editorial changes throughout. - TVN
03-10-01
APPROVED
R. R. Evans
Monica L. Poelking
Monica L. Poelking
Raymond Monnin
Thomas M. Hess
THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.
CURRENT CAGE CODE 67268
REV
SHEET
REV
E
SHEET
15
REV STATUS
OF SHEETS
REV
SHEET
EEEEEEEEDDEEE E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A
PREPARED BY
Greg A. Pitz
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
N. A. Hauck
APPROVED BY
N. A. Hauck
THIS DRAWING IS AVAILABLE
FOR USE BY ALL DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
87-04-29
REVISION LEVEL
AMSC N/A
E
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
MICROCIRCUIT, DIGITAL, ADVANCED CMOS, QUAD
2-INPUT NAND GATE, MONOLITHIC SILICON
SIZE
A
SHEET
CAGE CODE
14933
1 OF 15
5962-87549
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E410-03







5962-87549012 pdf, 数据表
TABLE I. Electrical performance characteristics – Continued.
1/ For tests not listed in the referenced MIL-STD-883, [e.g. VIH, VIL], utilize the general test procedure under the conditions
listed herein.
2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated shall be high level logic, low level logic, or open, except as follows:
a. VIC (pos) tests, the GND terminal can be open. TC = +25°C.
b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C.
c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the
circuit such that all current flows through the meter.
3/ RHA parts for device type 01 meet all levels M, D, P, L, R, and F of irradiation. However, these parts are only tested at the
“F” level. Pre and post irradiation values are identical unless otherwise specified in table I. When performing post
irradiation electrical measurements for any RHA level, TA = 25°C.
4/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I, as
applicable, at 3.0 V VCC 3.6 V and 4.5 V VCC 5.5 V.
5/ The VOH and VOL tests shall be tested at VCC = 3.0 V and 4.5 V. The VOH and VOL tests are guaranteed, if not tested, for
other values of VCC. Limits shown apply to operation at VCC = 3.3 V ±0.3 V and VCC = 5.0 V ±0.5 V. Tests with input
current at +50 mA or -50 mA are performed on only one input at a time with duration not to exceed 2 ms. Transmission
driving tests may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for
VIN = VIH minimum and VIL maximum.
6/ The VIH and VIL tests are not required if applied as forcing functions for VOH and VOL tests.
7/ The maximum limit for this parameter at 100 krads (Si) is 2 µA.
8/ Power dissipation capacitance (CPD) determines both the power consumption (PD) and dynamic current consumption (IS).
Where:
PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC)
IS = (CPD + CL) VCCf + ICC
f is the frequency of the input signal and CL is the external output load capacitance.
9/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of
each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth
table in figure 2 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified
devices. Allowable tolerances in accordance with MIL-STD-883 for the input voltage levels may be incorporated. For VOUT
measurements, L 0.3VCC and H 0.7VCC.
10/ For propagation delay tests, all paths must be tested. AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and
guaranteed by testing at VCC = 4.5 V. AC limits at VCC = 3.6 V are equal to limits at VCC = 3.0 V and guaranteed by testing
at VCC = 3.0 V. Minimum ac limits for VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum
limits to 1.5 ns.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
E
5962-87549
SHEET
8







5962-87549012 equivalent, schematic
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 03-10-01
Approved sources of supply for SMD 5962-87549 are listed below for immediate acquisition information only and shall be added to
MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or
deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to
and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
5962-8754901CA
5962-8754901DA
5962-87549012A
5962-8754901XA
5962-8754901XC
5962-8754901VXA
5962-8754901VXC
5962F8754901XA
5962F8754901XC
5962F8754901VXA
5962F8754901VXC
5962-87549022A
5962-8754902EA
5962-8754902FA
Vendor
CAGE
number
27014
01295
27014
01295
27014
01295
3/
3/
3/
3/
F8859
F8859
F8859
F8859
3/
3/
3/
Vendor
similar
PIN 2/
54AC00DMQB
SNJ54AC00J
54AC00FMQB
SNJ54AC00W
54AC00LMQB
SNJ54AC00FK
54AC00K02Q
54AC00K01Q
54AC00K02V
54AC00K01V
RHFAC00K02Q
RHFAC00K01Q
RHFAC00K02V
RHFAC00K01V
SNJ54AC11000FK
SNJ54AC11000J
SNJ54AC11000W
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer
listed for that part. If the desired lead finish is not listed,
contact the vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance
requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
Vendor name
and address
27014
National Semiconductor
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
F8859
ST Microelectronics
3 rue de Suisse
BP4199
35041 RENNES cedex2 - FRANCE
01295
Texas Instruments Incorporated
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.










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