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PDF ( 数据手册 , 数据表 ) W65C22S

零件编号 W65C22S
描述 VIA
制造商 Western Design
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W65C22S 数据手册, 描述, 功能
The Western Design Center, Inc.
May 2003
1
W65C22S Data Sheet
W65C22S
Versatile Interface Adapter (VIA)
DATA SHEET
The Western Design Center, Inc., 2003. All rights reserved
WDC







W65C22S pdf, 数据表
The Western Design Center, Inc.
W65C22S Data Sheet
Table 1-1 W65C22S Memory Map of Internal Registers
Register
Number
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RS Coding
Register
Designation
RS3 RS2
RS1 RS0
Write
Description
Read
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
0
0 ORB/IRB
Output Register "B"
Input Register "B"
0
1 ORA/IRA
Output Register "A"
Input Register "A"
1 0 DDRB
Data Direction Register "B"
1 1 DDRA
Data Direction Register "A"
0 0 T1C-L
T1 Low-Order Latches
T1 Low-Order Counter
0 1 T1C-H
T1 High-Order Counter
1 0 T1L-L
T1 Low-Order Latches
1 1 T1L-H
T1 High-Order Latches
0 0 T2C-L
T2 Low-Order Latches
T2 Low-Order Counter
0 1 T2C-H
T2 High-Order Counter
1 0 SR
Shift Register
1 1 ACR
Auxiliary Control Register
0 0 PCR
Peripheral Control Register
0 1 IFR
Interrupt Flag Register
1 0 IER
Interrupt Enable Register
1 1 ORA/IRA
Same as Reg 1 except no "Handshake"
1.1. Peripheral Data Ports
Both PA and PB operate in conjunction with a Data Direction Register (DDRA or DDRB). Under program control, the
DDRA and DDRB specify which lines within the port bus are to be designated as inputs or outputs. A Logic 0 in any
bit position of the register will cause the corresponding line to serve as an input, while a Logic 1 will cause the line to
serve as an output.
When a line is programmed as an output, it is controlled by a corresponding bit in the Output Register (ORA & ORB).
A Logic 1 in the ORA or ORB will cause the corresponding output line to go high, while a Logic 0 will cause the line to
go low. Under program control, data is written into the ORA or ORB bit positions corresponding to the output lines
which have been programmed as outputs. Should data be written into bit positions corresponding to lines which have
been programmed as input, the output lines will be unaffected.
The Western Design Center, Inc.
W65C22S Datasheet
8







W65C22S equivalent, schematic
The Western Design Center, Inc.
W65C22S Data Sheet
Table 1-8 Auxiliary Control Register Format and Operation ($0B)
76
T1 Timer Control
7
0
0
1
1
5 432
T2 Timer
Control
Shift Register Control
T1 Timer Control
6 Operation
PB7
1
PB
0 Timed interrupt each time T1
is loaded
Disabled
1 Continuous interrupts
0 Timed interrupt each time T1 One shot output
is loaded
1 Continuous interrupts
Square wave output
0 ACR
PA
T2 Timer Control
5 Operation
0 Timed interrupt
1 Count down with pulses on PB6
Shift Register Control
4 3 2 Operation
0 0 0 Disabled
0 0 1 Shift in under control of T2
0 1 0 Shift in under control of PHI2
0 1 1 Shift in under control of external clock
1 0 0 Shift out free-running at T2 rate
1 0 1 Shift out under control of T2
1 1 0 Shift out under control of PHI2
1 1 1 Shift out under control of external clock
Latch Enable/Disable
1 0 Operation
0 0 Disable
1 1 Enable latching
The Western Design Center, Inc.
W65C22S Datasheet
16










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