DataSheet8.cn


PDF ( 数据手册 , 数据表 ) ZL30106

零件编号 ZL30106
描述 SONET/SDH/PDH Network Interface DPLL
制造商 Zarlink
LOGO Zarlink LOGO 


1 Page

No Preview Available !

ZL30106 数据手册, 描述, 功能
ZL30106
SONET/SDH/PDH
Network Interface DPLL
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between inputs and outputs
• Supports output wander and jitter generation
specifications for SONET/SDH and PDH
interfaces
• Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs:
- 2.048 MHz (E1), 16.384 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
- 19.44 MHz (SONET/SDH)
- 1.544 MHz (DS1) and 3.088 MHz
- a choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Provides automatic entry into Holdover and return
from Holdover
• Manual and automatic hitless reference switching
• Provides lock, holdover and accurate reference
fail indication
October 2004
Ordering Information
ZL30106QDG 64 pin TQFP
-40°C to +85°C
• Selectable loop filter bandwidth of 29 Hz or
922 Hz
• Less than 24 psrms intrinsic jitter on the
19.44 MHz output clock, compliant with GR-253-
CORE OC-3 and G.813 STM-1 specifications
• Less than 0.6 nspp intrinsic jitter on all PDH output
clocks and frame pulses
• Selectable external master clock source: clock
oscillator or crystal
• Simple hardware control interface
Applications
• Line card synchronization for SONET/SDH and
PDH systems
• Wireless base-station Network Interface Card
• AdvancedTCA™ and H.110 line cards
OSCi OSCo TIE_CLR
BW_SEL LOCK
OUT_SEL2
REF0
REF_SYNC0
REF1
REF_SYNC1
REF2
REF_FAIL0
REF_FAIL1
REF_FAIL2
APP_SEL1:0
REF_SEL1:0
RST
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
SDH
Synthesizer
Programmable
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
TRST
MODE_SEL1:0 HMS
HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.







ZL30106 pdf, 数据表
ZL30106
Data Sheet
2.2 Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
Description
GND
Ground. 0 V
VCORE
LOCK
Positive Supply Voltage. +1.8 VDC nominal
Lock Indicator (Output). This output goes to a logic high when the PLL is frequency
locked to the selected input reference.
HOLDOVER Holdover (Output). This output goes to a logic high whenever the PLL goes into
holdover mode.
REF_FAIL0 Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0
reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that
it is exhibiting abrupt phase or frequency changes.
REF_FAIL1 Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1
reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that
it is exhibiting abrupt phase or frequency changes.
REF_FAIL2 Reference 2 Failure Indicator (Output). A logic high at this pin indicates that the REF2
reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that
it is exhibiting abrupt phase or frequency changes.
TDO
Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge
of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
TMS
Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to VDD. If this pin is not used then it should be
left unconnected.
TRST
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that
the device is in the normal functional state. This pin is internally pulled up to VDD. If
this pin is not used then it should be connected to GND.
TCK
Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it
should be pulled down to GND.
VCORE
GND
Positive Supply Voltage. +1.8 VDC nominal
Ground. 0 V
AVCORE
TDI
Positive Analog Supply Voltage. +1.8 VDC nominal
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this
pin. This pin is internally pulled up to VDD. If this pin is not used then it should be left
unconnected.
HMS
Hitless Mode Switching (Input). The HMS input controls phase accumulation during the
transition from Holdover or Freerun mode to Normal mode on the same reference. A logic
low at this pin will cause the ZL30106 to maintain the delay stored in the TIE corrector
circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high
on this pin will cause the ZL30106 to measure a new delay for its TIE corrector circuit
thereby minimizing the output phase movement when it transitions from Holdover or
Freerun mode to Normal mode.
MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode of
operation, see Table 4 on page 21.
MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description.
8
Zarlink Semiconductor Inc.







ZL30106 equivalent, schematic
ZL30106
Data Sheet
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 24. The speed of the phase alignment correction is limited by the loop filter bandwidth. Convergence is
always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case the output clocks
will always align with the selected input reference. This is illustrated in Figure 9.
REF0
TIE_CLR = 0
locked to REF0
REF0
TIE_CLR = 1
locked to REF0
REF1
REF1
Output
Clock
REF0
REF1
locked to REF1
Output
Clock
REF0
REF1
locked to REF1
Output
Clock
Output
Clock
Figure 9 - Timing Diagram of Hitless Reference Switching
The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal
mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value
thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode
(see Figure 10). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE
circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode.
This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the
input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30106 is
always hitless unless TIE_CLR is kept low continuously.
16
Zarlink Semiconductor Inc.










页数 48 页
下载[ ZL30106.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
ZL30100T1/E1 System SynchronizerZarlink Semiconductor Inc
Zarlink Semiconductor Inc
ZL30101T1/E1 Stratum 3 System SynchronizerZarlink Semiconductor Inc
Zarlink Semiconductor Inc
ZL30102T1/E1 Stratum 4/4E Redundant System Clock SynchronizerZarlink Semiconductor
Zarlink Semiconductor
ZL30105T1/E1/SDH Stratum 3 Redundant System Clock SynchronizerZarlink Semiconductor
Zarlink Semiconductor

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap