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PDF ( 数据手册 , 数据表 ) ST24W16

零件编号 ST24W16
描述 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
制造商 ST Microelectronics
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ST24W16 数据手册, 描述, 功能
ST24C16, ST25C16
ST24W16, ST25W16
16 Kbit Serial I2C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 16 Kbit I2C bus
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver-
sion and "W" for hardware Write Control version.
The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
Table 1. Signal Names
PRE
PB0, PB1
SDA
SCL
MODE
WC
VCC
VSS
Write Protect Enable
Protect Block Select
Serial Data Address Input/Output
Serial Clock
Multybyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
VCC
2
PB0-PB1
PRE
SCL
MODE/WC*
ST24x16
ST25x16
SDA
VSS
AI00866B
Note: WC signal is only available for ST24/25W16 products.
February 1999
1/17







ST24W16 pdf, 数据表
ST24/25C16, ST24/25W16
Figure 6. I2C Bus Protocol
SCL
SDA
START
CONDITION
SDA
SDA
INPUT CHANGE
STOP
CONDITION
SCL
SDA
12
MSB
START
CONDITION
3
SCL
SDA
12
MSB
3
789
ACK
789
ACK
STOP
CONDITION
AI00792
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x16
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x16
samples the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24/25x16,
the master must initiate a START condition. The 8
bits sent after a START condition are made up of a
device select of 4 bits that identifie the device type
(1010), 3 Block select bits and one bit for a READ
(RW = 1) or WRITE (RW = 0) operation.
There are three modes both for read and write.
They are summarised in Table 4 and described
hereafter. A communication between the master
and the slave is ended with a STOP condition.
8/17







ST24W16 equivalent, schematic
ST24/25C16, ST24/25W16
SO8 - 8 lead Plastic Small Outline, 150 mils body width
Symb
Typ
mm
Min Max
inches
Typ Min Max
A
1.35 1.75
0.053
0.069
A1
0.10 0.25
0.004
0.010
B
0.33 0.51
0.013
0.020
C
0.19 0.25
0.007
0.010
D
4.80 5.00
0.189
0.197
E
3.80 4.00
0.150
0.157
e 1.27 –
– 0.050 –
H
5.80 6.20
0.228
0.244
h
0.25 0.50
0.010
0.020
L
0.40 0.90
0.016
0.035
α
0° 8°
0° 8°
N8
8
CP 0.10 0.004
B
e
D
A
CP
N
EH
1
SO-a
Drawing is not to scale.
16/17
h x 45˚
C
A1 α L










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