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PDF ( 数据手册 , 数据表 ) QL4009

零件编号 QL4009
描述 Quick RAM
制造商 QuickLogic
LOGO QuickLogic LOGO 


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QL4009 数据手册, 描述, 功能
QL4009 - QuickRAMTM
9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM
QL4009 - QuickRAM
DEVICE HIGHLIGHTS
Device Highlights
High Performance & High Density
s 9,000 Usable PLD Gates with 82 I/Os
s 300 MHz 16-bit Counters, 400 MHz Datapaths,
160+ MHz FIFOs
s 0.35µm four-layer metal non-volatile CMOS process for
smallest die sizes
High Speed Embedded SRAM
s 8 dual-port RAM modules, organized in user-configurable
1,152 bit blocks
s 5ns access times, each port independently accessible
s Fast and effecient for FIFO, RAM, and ROM functions
Easy to Use / Fast Development Cycles
s 100% routable with 100% utilization and complete
pin-out stability
s Variable-grain logic cells provide high performance and
100% utilization
s Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilities
s Interfaces with both 3.3 volt and 5.0 bolt devices
s PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4
speed grades
s Full JTAG boundary scan
s Registered I/O cells with individually controlled clocks and
output enables
8 RAM
Blocks
} 160
High Speed
Logic Cells
Interface
FIGURE 1. QuickRAM Block Diagram
ARCHITECTURE OVERVIEW
The QuickRAM family of ESPs (Embedded Standard
Products) offers FPGA logic in combination with Dual-
Port SRAM modules. The QL4009 is a 9,000 usable
PLD gate member of the QuickRAM family of ESPs.
QuickRAM ESPs are fabricated on a 0.35mm four-
layer metal process using QuickLogic’s patented
ViaLinkTM technology to provide a unique combina-
tion of high performance, high density, low cost, and
extreme ease-of-use.
The QL4009 contains 160 logic cells and 8 dual port
RAM modules (see Figure 1). Each RAM module has
1,152 RAM bits, for a total of 9,216 bits. RAM Mod-
ules are Dual Port (one read port, one write port) and
can be configured into one of four modes: 64 (deep)
x18 (wide), 128x9, 256x4, or 512x2 (see Figure 2).
With a maximum of 82 I/Os, the QL4009 is available
in 68-pin PLCC, 84-pin PLCC, and 100-pin TQFP
packages.
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules (see Figure
3). This approach allows up to 512-deep configura-
tions as large as 16 bits wide in the smallest Quick-
RAM device and 44 bits wide in the largest device.
QL4009 Rev B
6-11







QL4009 pdf, 数据表
QL4009 - QuickRAMTM
Symbol
TSRA
THRA
TSRE
THRE
TRCRD
RAM Cell Synchronous Read Timing
Parameter
RA Setup Time to RCLK
RA Hold Time to RCLK
RE Setup Time to RCLK
RE Hold Time to RCLK
RCLK to RD [5]
Propagation Delays (ns)
Fanout
1234
1.0 1.0 1.0 1.0
0.0 0.0 0.0 0.0
1.0 1.0 1.0 1.0
0.0 0.0 0.0 0.0
4.0 4.3 4.6 4.9
8
1.0
0.0
1.0
0.0
6.1
Symbol
RPDRD
RAM Cell Asynchronous Read Timing
Parameter
RA to RD [5]
Propagation Delays (ns)
Fanout
1234
3.0 3.3 3.6 3.9
8
5.1
Symbol
TIN
TINI
TISU
TIH
TlCLK
TlRST
TlESU
TlEH
Input-Only/Clock Cells
Parameter
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Propagation Delays (ns)
Fanout [5]
1 2 3 4 8 12 24
1.5 1.6 1.8 1.9 2.4 2.9 4.4
1.6 1.7 1.9 2.0 2.5 3.0 4.5
3.1 3.1 3.1 3.1 3.1 3.1 3.1
0.0 0.0 0.0 0.0 0.0 0.0 0.0
0.7 0.8 1.0 1.1 1.6 2.1 3.6
0.6 0.7 0.9 1.0 1.5 2.0 3.5
2.3 2.3 2.3 2.3 2.3 2.3 2.3
0.0 0.0 0.0 0.0 0.0 0.0 0.0
Symbol
tACK
tGCKP
tGCKB
Clock Cells
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1
1.2
0.7
0.8
Propagation Delays (ns)
Loads per Half Column [7]
2 3 4 8 10
1.2 1.3 1.3 1.5 1.6
0.7 0.7 0.7 0.7 0.7
0.8 0.9 0.9 1.1 1.2
11
1.7
0.7
1.3
Notes:
[7] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44
half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads
per half column.
6-18
18 Preliminary














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