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PDF ( 数据手册 , 数据表 ) DG187AA

零件编号 DG187AA
描述 High-Speed Drivers with JFET Switch
制造商 Intersil Corporation
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DG187AA 数据手册, 描述, 功能
Semiconductor
DG181 thru DG191
April 1999
Features
• Constant
ON-PROeDSDsDGiSGsG1OtI1Ba189Bn9L40cS1,E:e:ODDSHfGLoGUIEr1-B45T8S00S5Ei34g:T,3PnHIHT,aRIHUlI-Os-55IT-0Dt00Eo4U539P1±9C,,1R0HTI0,OHIVI-HD55(150UD504CG145T1382,
DG185, DG188, DG191), to ±7.5V (All Devices)
±15V Power Supplies
• <2nA Leakage from Signal Channel in Both ON and
OFF States
• TTL, DTL, RTL Direct Drive Compatibility
• tON, tOFF <150ns, Break-Before-Make Action
• Cross-Talk and Open Switch Isolation >50dB at 10MHz
(75Load)
High-Speed Drivers with JFET Switch
Description
The DG181 thru DG191 series of analog gates consist of 2
or 4 N-channel junction-type field-effect transistors (JFET)
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8V to 2V) to control the
ON-OFF state of each switch. The driver is designed to
provide a turn-off speed which is faster than turn-on speed,
so that break-before-make action is achieved when
switching from one channel to another. In the ON state, each
switch conducts current equally well in both directions. In the
OFF condition, the switches will block voltages up to 20V
peak-to-peak. Switch-OFF input-output isolation 50dB at
10MHz, due to the low output impedance of the FET-gate
driving circuit.
Functional Diagrams (Typical Channel)
DG186, DG187, DG188 - ONE AND TWO CHANNEL
SPDT AND SPST CIRCUIT CONFIGURATION
VL V+
DG183, DG184, DG185 - TWO CHANNEL DPST
CIRCUIT CONFIGURATION
VL V+
IN
GND V-
S1 IN
D1
S2
D2
GND
V-
S
D
S
D
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1999
1
File Number 3114.4







DG187AA pdf, 数据表
DG181 Series
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
-A- -D-
E
-B-
bbb S C A - B S D S
c1 LEAD FINISH
BASE
METAL
(c)
b1
MM
(b)
SECTION A-A
BASE
PLANE
SEATING
PLANE
D
S1
b2
b
AA
e
ccc M C A - B S D S
S2 Q
-C- A
L
eA
eA/2
c
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
- 0.200 - 5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
- 0.840 - 21.34
-
E
0.220
0.310
5.59
7.87
-
e 0.100 BSC
2.54 BSC
-
eA 0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1 0.005 - 0.13 - 6
S2 0.005 - 0.13
α 90o 105o 90o
-
105o
7
-
aaa
- 0.015 - 0.38
-
bbb
- 0.030 - 0.76
-
ccc
- 0.010 - 0.25
-
M
-
0.0015
-
0.038
2
N 16
16 8
Rev. 0 4/94
8














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