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PDF ( 数据手册 , 数据表 ) 28F200BV-TB

零件编号 28F200BV-TB
描述 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
制造商 Intel
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28F200BV-TB 数据手册, 描述, 功能
E
SEE NEW DESIGN RECOMMENDATIONS
REFERENCE ONLY
2-MBIT SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B
n Intel SmartVoltage Technology
5 V or 12 V Program/Erase
3.3 V or 5 V Read Operation
n Very High-Performance Read
5 V: 60 ns Access Time
3 V: 110 ns Access Time
n Low Power Consumption
Max 60 mA Read Current at 5 V
Max 30 mA Read Current at
3.3 V–3.6 V
n x8/x16-Selectable Input/Output Bus
28F200 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F002B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
n Extended Temperature Operation
–40 °C to +85 °C
n Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-, 48-, 56-Lead TSOP
44-Lead PSOP
n Footprint Upgradeable to 4-Mbit and
8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
New Design Recommendations:
For new 2.7 V–3.6 V VCC designs with this device, Intel recommends using the Smart 3 Advanced Boot
Block. Reference Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family datasheet,
order number 290580.
For new 5 V VCC designs with this device, Intel recommends using the 2-Mbit Smart 5 Boot Block. Reference
Smart 5 Flash Memory Family 2, 4, 8 Mbit datasheet, order number 290599.
These documents are also available at Intel’s website, http://www.intel.com/design/flcomp.
December 1997
Order Number: 290531-005







28F200BV-TB pdf, 数据表
2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
A[17:1]
CS#
RD#
WR#
i386™ EX CPU
(25 MHz)
D[15:0]
A[16:0]
CE#
OE#
WE#
28F200BV-60
D[15:0]
RESET
RP#
RESET
NOTE:
A data bus buffer may be needed for processor speeds above 25 MHz.
Figure 1. 28F200 Interface to Intel386™ EX Microprocessor
0530_01
A[16:17]
A8-A15
80C188EB
ALE
AD0-AD7
ADDRESS
LATCHES
LE
ADDRESS
LATCHES
LE
A0 -A17
28F002-T
UCS#
WR#
RD#
RESIN#
P1.X
System Reset
DQ0-DQ7
CE#
VCC
10K
WE#
OE#
RP#
VCC
VPP
P1.X
WP#
0530_02
Figure 2. 28F002B Interface to Intel80C188EB 8-Bit Embedded Microprocessor
8 SEE NEW DESIGN RECOMMENDATIONS







28F200BV-TB equivalent, schematic
2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode
Notes RP# CE# OE# WE# A9
A0 VPP
Read
1,2,3 VIH VIL VIL VIH
X
X
X
Output Disable
VIH VIL VIH VIH
X
X
X
Standby
VIH VIH
X
X
X
X
X
Deep Power-Down 9 VIL X X X X X X
Intelligent Identifier
(Mfr)
4 VIH VIL VIL VIH VID VIL X
Intelligent Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH
X
Write
6,7,8 VIH VIL VIH VIL
X
X
X
DQ0–15
DOUT
High Z
High Z
High Z
0089 H
See
Table 5
DIN
Mode
Read
Output
Disable
Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Notes RP# CE# OE# WE# A9
A0 A–1 VPP
1,2,3 VIH VIL VIL VIH
X
X
X
X
VIH VIL VIH VIH
X
X
X
X
DQ0–7
DOUT
High Z
DQ8–14
High Z
High Z
Standby
VIH VIH
X
X
X
X
X
X High Z High Z
Deep Power-
9
VIL X
X
X
X
X
X
X High Z High Z
Down
Intelligent
Identifier (Mfr)
4
VIH VIL VIL VIH VID VIL
X
X 89H High Z
Intelligent
Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH X
X See High Z
Table
5
Write
6,7,8 VIH VIL VIH VIL
X
X
X
X
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP.
3. See DC Characteristics for VPPLK, VPPH1, VPPH2, VHH, VID voltages.
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A16 = X, A1–A17 = X.
5. See Table 5 for device IDs.
6. Refer to Table 7 for valid DIN during a write operation.
7. Command writes for block erase or word/byte program are only executed when VPP = VPPH1 or VPPH2.
8. To program or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4.
9. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
High Z
16 SEE NEW DESIGN RECOMMENDATIONS










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