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PDF ( 数据手册 , 数据表 ) P51XAG30KFBD

零件编号 P51XAG30KFBD
描述 XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless / watchdog / 2 UARTs
制造商 NXP Semiconductors
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P51XAG30KFBD 数据手册, 描述, 功能
INTEGRATED CIRCUITS
XA-G3
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification
Supersedes data of 1998 Aug 14
IC25 Data Handbook
1999 Apr 07
Philips
Semiconductors







P51XAG30KFBD pdf, 数据表
Philips Semiconductors
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification
XA-G3
NAME
DESCRIPTION
SFR
ADDRESS MSB
BIT FUNCTIONS AND ADDRESSES
RESET
LSB VALUE
357 356 355 354 353 352 351 350
SWR* Software Interrupt Request
42A — SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00
2C7 2C6 2C5 2C4 2C3 2C2 2C1 2C0
T2CON* Timer 2 control register
418 TF2 EXF2 RCLK0 TCLK0 EXEN2 TR2 C/T2 CP/RL2 00
2CF 2CE 2CD 2CC 2CB 2CA 2C9 2C8
T2MOD* Timer 2 mode control
419 — — RCLK1 TCLK1 — — T2OE DCEN 00
TH2
TL2
T2CAPH
T2CAPL
Timer 2 high byte
Timer 2 low byte
Timer 2 capture register,
high byte
Timer 2 capture register,
low byte
459
458
45B
45A
00
00
00
00
287 286 285 284 283 282 281 280
TCON* Timer 0 and 1 control register
410 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00
TH0 Timer 0 high byte
TH1 Timer 1 high byte
TL0 Timer 0 low byte
TL1 Timer 1 low byte
451
453
450
452
00
00
00
00
TMOD Timer 0 and 1 mode control
45C GATE C/T
M1
M0 GATE C/T
M1
M0
00
28F 28E 28D 28C 28B 28A 289 288
TSTAT* Timer 0 and 1 extended status
411
— T1OE — T0OE 00
2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8
WDCON* Watchdog control register
41F PRE2 PRE1 PRE0 —
WDRUN WDTOF Note 6
WDL
Watchdog timer reload
45F
00
WFEED1 Watchdog feed 1
45D
x
WFEED2 Watchdog feed 2
45E
x
NOTES:
* SFRs are bit addressable.
1. At reset, the BCR register is loaded with the binary value 0000 0a11, where “a” is the value on the BUSW pin. This defaults the address bus
size to 20 bits since the XA-G3 has only 20 address lines.
2. SFR is loaded from the reset vector.
3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.
4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is 0.
5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the
condition found on the EA pin. Thus all PnCFGA registers will contain FF and PnCFGB registers will contain 00. When the XA begins
execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. The
PnCFGA and PnCFGB register contents will reflect this difference.
6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
7. The XA-G3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8-bit operations. Attempts to
write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.
1999 Apr 07
8







P51XAG30KFBD equivalent, schematic
Philips Semiconductors
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification
XA-G3
Serial Port Control Register
The serial port control and status register is the Special Function
Register SnCON, shown in Figure 12. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n
and RI_n).
TI Flag
In order to allow easy use of the double buffered UART transmitter
feature, the TI_n flag is set by the UART hardware under two
conditions. The first condition is the completion of any byte
transmission. This occurs at the end of the stop bit in modes 1, 2, or
3, or at the end of the eighth data bit in mode 0. The second
condition is when SnBUF is written while the UART transmitter is
idle. In this case, the TI_n flag is set in order to indicate that the
second UART transmitter buffer is still available.
Typically, UART transmitters generate one interrupt per byte
transmitted. In the case of the XA UART, one additional interrupt is
generated as defined by the stated conditions for setting the TI_n
flag. This additional interrupt does not occur if double buffering is
bypassed as explained below. Note that if a character oriented
approach is used to transmit data through the UART, there could be
a second interrupt for each character transmitted, depending on the
timing of the writes to SBUF. For this reason, it is generally better to
bypass double buffering when the UART transmitter is used in
character oriented mode. This is also true if the UART is polled
rather than interrupt driven, and when transmission is character
oriented rather than message or string oriented. The interrupt occurs
at the end of the last byte transmitted when the UART becomes idle.
Among other things, this allows a program to determine when a
message has been transmitted completely. The interrupt service
routine should handle this additional interrupt.
The recommended method of using the double buffering in the
application program is to have the interrupt service routine handle a
single byte for each interrupt occurrence. In this manner the
program essentially does not require any special considerations for
double buffering. Unless higher priority interrupts cause delays in
the servicing of the UART transmitter interrupt, the double buffering
will result in transmitted bytes being tightly packed with no
intervening gaps.
9-bit Mode
Please note that the ninth data bit (TB8) is not double buffered. Care
must be taken to insure that the TB8 bit contains the intended data
at the point where it is transmitted. Double buffering of the UART
transmitter may be bypassed as a simple means of synchronizing
TB8 to the rest of the data stream.
Bypassing Double Buffering
The UART transmitter may be used as if it is single buffered. The
recommended UART transmitter interrupt service routine (ISR)
technique to bypass double buffering first clears the TI_n flag upon
entry into the ISR, as in standard practice. This clears the interrupt
that activated the ISR. Secondly, the TI_n flag is cleared
immediately following each write to SnBUF. This clears the interrupt
flag that would otherwise direct the program to write to the second
transmitter buffer. If there is any possibility that a higher priority
interrupt might become active between the write to SnBUF and the
clearing of the TI_n flag, the interrupt system may have to be
temporarily disabled during that sequence by clearing, then setting
the EA bit in the IEL register.
Note Regarding Older XA-G3 Devices
Older versions of the XA-G30, XA-G37, and XA-G35 emulation
bondout devices do not have the double buffering feature enabled.
Contact factory for details.
1999 Apr 07
16










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