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PDF ( 数据手册 , 数据表 ) ORT4622

零件编号 ORT4622
描述 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
制造商 Agere Systems
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ORT4622 数据手册, 描述, 功能
Preliminary Data Sheet
March 2000
ORCA® ORT4622 Field-Programmable System Chip (FPSC)
Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiver
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Embedded Core Features
s Implemented in an ORCA Series 3 FPGA array.
s Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
s No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock, and
a frame pulse.
s High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without
external clocks.
Table 1. ORCA ORT4622—Available FPGA Logic
s HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
s Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
s LVDS I/Os compliant with EIA*-644, support hot
insertion.
s 8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
s On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6 UIP-P at 250 kHz).
s Powerdown option of HSI receiver on a per-
channel basis.
s Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
s In-Band management and configuration.
s Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
s Built-in boundry scan (IEEE1149.1 JTAG).
s FIFOs align incoming data across all four channels
for STS-48 (2.5 Gbits/s) operation (in quad STS-12
format).
s 1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for
protection switching applications.
* EIA is a registered trademark of Electronic Industries Associa-
tion.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
ORT4622
Usable
System
Gates
60K—120K
Number of
LUTs
4032
Number of
Registers
5304
Max User
RAM
64K
Max User
I/Os
Array Size
Number of
PFUs
259 18 x 28 504
‡ The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to
a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the
four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.







ORT4622 pdf, 数据表
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
ORT4622 Overview
Device Layout
The ORT4622 FPSC provides a high-speed backplane
transceiver combined with FPGA logic. The device is
based on a 2.5 V 3.3 V I/O OR3L125B FPGA. The
OR3L125B has a 28 x 28 array of programmable logic
cells (PLCs). For the ORT4622, the bottom ten rows of
PLCs in the array were replaced with the embedded
backplane transceiver core. The ORT4622 embedded
core comprises the HSI macrocell, the synchronous
transport module (STM) macrocell, a CPU interface,
and LVDS I/Os. The four full-duplex channels perform
data transfer, scrambling/descrambling and framing at
the rate of 622 Mbits/s. Figure 1 shows the ORT4622
block diagram.
Table 2 shows a schematic view of the ORT4622. The
upper portion of the device is an 18 x 28 array of PLCs
surrounded on the left, top, and right by programmable
input/output cells (PICs). At the bottom of the PLC
array are the core interface cells (CICs) connecting to
the embedded core region. The embedded core region
contains the backplane transceiver functionality of the
device. It is surrounded on the left, bottom, and right by
backplane transceiver dedicated I/Os as well as power
and special function FPGA pins. Also shown are the
interquad routing blocks (hIQ, vIQ) present in the
Series 3 FPGA devices. System-level functions
(located in the corners of the PLC array), routing
resources, and configuration RAM are not shown in
Table 2.
Backplane Transceiver Interface
The advantage of the ORT4622 FPSC is to bring spe-
cific networking functions to an early market presence
with programmable logic in FPGA system.
The 622 Mbits/s backplane transceiver core allows the
ORT4622 to communicate across a backplane or on a
given board at an aggregate speed of 2.5 Gbits/s, pro-
viding a physical medium for high-speed asynchronous
serial data transfer between system devices. This
device is intended for, but not limited to, connecting ter-
minal equipment in SONET/SDH and ATM systems.
For networking applications, the ORT4622 offers a
pseudo SONET framer and scrambler/descrambler
interface capable of frame synchronization and inser-
tion/extraction of selectable transport overhead bytes
and SONET scrambling and descrambling for four
STS-12 (622 Mbits/s) channels. The channels are syn-
chronized to each other by a user-provided 8 kHz
frame pulse. The ORT4622 also provides STS-48
(2.5 Gbits/s) operation across all four channels where
each channel is in STS-12 format. The pseudo-SONET
framer of OR4622 is designed with a reduced set of the
SONET framing algorithm. The pointer processing
capability is more suitable for low error rate intersystem
data communication, particular for backplane trans-
ceiver applications. Figure 2 shows the architecture of
the ORT4622 backplane transceiver core.
622 Mbits/s
DATA
4
4 FULL-
DUPLEX
SERIAL
CHANNELS
4
622 Mbits/s
DATA
LVDS
I/Os
HSI STM
• CLOCK/DATA
RECOVERY
BYTE-
WIDE
DATA
• POINTER MOVER
• SCRAMBLING
• FIFO ALIGNMENT
• TOH PROCESSOR
FPGA LOGIC
Figure 1. ORCA ORT4622 Block Diagram
STANDARD
FPGA
I/Os
5-8113(F)
8 LLuucceennt tTTeecchhnnoolologgieiessInIncc..







ORT4622 equivalent, schematic
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
Backplane Transceiver Core Detailed
Description (continued)
Transport Overhead for In Band Communication
The TOH byte can be used for In Band configuration,
service, and management since it is carried along the
same channel as data. In ORT4622, In Band signaling
can be efficiently utilized, since the total cost of over-
head is only 3.3%.
Transport Overhead Insertion (Serial Link)
The TOH serial links are used to insert TOH bytes into
the transmit data. The transmit TOH data and
TOH_CLK_EN get retimed by TOH_CLK in order to
meet setup and hold specifications of the device.
The retimed TOH data is shifted into a 288-bit (36-byte
by 8-bit) shift register and then multiplexed as an 8-bit
bus to be inserted into the byte-wide data stream.
Insertion from these serial links or pass-through of
TOH from the byte-wide data is under software control.
Transport Overhead Byte Ordering
(FPGA to Backplane)
In the transparent mode, SPE and TOH data received
on parallel input bus is transferred, unaltered, to the
serial LVDS output. However, B1 byte of STS#1 is
always replaced with a new calculated value (the 11
bytes following B1 are replaced with all zeros). Also,
A1 and A2 bytes of all STS-1s are always regenerated.
TOH serial port in not used in the transparent mode of
operation.
In the TOH insert mode, SPE bytes are transferred,
unaltered, from the input parallel bus to the serial LVDS
output. On the other hand, TOH bytes are received
from the serial input port and are inserted in the STS-
12 frame before being sent to the LVDS output.
Although all TOH bytes from the 12 STS-1s are trans-
ferred into the device from each serial port, not all of
them get inserted in the frame. There are three hard-
coded exceptions to the TOH byte insertion:
s Framing bytes (A1/A2 of all STS-1s) are not inserted
from the serial input bus. Instead, they can always be
regenerated.
s Parity byte (B1 of STS#1) is not inserted from the
serial input bus. Instead, it is always recalculated
(the 11 bytes following B1 are replaced with all
zeros).
s Pointer bytes (H1/H2/H3 of all STS-1s) are not
inserted from the serial input bus. Instead, they
always flow transparently from parallel input to LVDS
output.
16
In addition to the above hard-coded exceptions, the
source of some TOH bytes can be further controlled by
software. When configured to be in pass-through
mode, the specific bytes must flow transparently from
the parallel input. Note that blocks of 12 STS-1 bytes
forming an STS-12 are controlled as a whole. There
are 15 software controls per channel, as listed below:
s Source of K1 and K2 bytes of the 12 STS-1s
(24 bytes) is specified by a control bit (per channel
control).
s Source of S1 and M0 bytes of the 12 STS-1s
(24 bytes) is specified by a control bit (per channel
control).
s Source of E1, F1, E2 bytes of the STS-1s (36 bytes)
is specified by a control it (per channel control).
s Source of D1 bytes of the STS-1s (12 bytes) is spec-
ified by a control bit (per channel control).
s Source of D2 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D3 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D4 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D5 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D6 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D7 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D8 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D9 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D10 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D11 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
s Source of D12 bytes of the 12 STS-1s (12 bytes) is
specified by a control bit (per channel control).
TOH reconstruction is dependent on the transmitter
mode of operation. In the transparent mode of opera-
tion, TOH bytes on LVDS output are as shown in Table
3.
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