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PDF ( 数据手册 , 数据表 ) OR2C06A

零件编号 OR2C06A
描述 Field-Programmable Gate Arrays
制造商 Agere Systems
LOGO Agere Systems LOGO 


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OR2C06A 数据手册, 描述, 功能
Data Sheet
June 1999
ORCA® Series 2
Field-Programmable Gate Arrays
Features
s High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
s High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
s Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
s Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
s Eight 3-state buffers per PFU for on-chip bus structures
s Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
s Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
s Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
s Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
s Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
Table 1. ORCA Series 2 FPGAs
s Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacrificing
performance
s Upward bit stream compatible with the ORCA ATT2Cxx/
ATT2Txx series of devices
s Pinout-compatible with new ORCA Series 3 FPGAs
s TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
s Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
s Built-in boundary scan (IEEE*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
s Multiple configuration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
s Full PCI bus compliance for all devices
s Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ORCA Foundry
Development System support (for back-end implementa-
tion)
s New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI sys-
tems
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A/OR2T12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
Usable
Gates*
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
# LUTs Registers
400
576
784
1024
1296
1600
2304
3600
400
576
724
1024
1296
1600
2304
3600
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
Array Size
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.







OR2C06A pdf, 数据表
ORCA Series 2 FPGAs
Data Sheet
June 1999
Programmable Logic Cells (continued)
The LUT ripple mode operation offers standard arith-
metic functions, such as 4-bit adders, subtractors,
adder/subtractors, and counters. In the ORCA
Series 2, there are two new ripple modes available.
The first new mode is a 4 x 1 multiplier, and the second
is a 4-bit comparator. These new modes offer the
advantages of faster speeds as well as denser logic
capabilities.
When the LUT is configured to operate in the memory
mode, a 16 x 2 asynchronous memory fits into an
HLUT. Both the MA and MB modes were available in
previous ORCA architectures, and each mode can be
configured in an HLUT separately. In the Series 2,
there are two new memory modes available. The first is
a 16 x 4 synchronous single-port memory (SSPM), and
the second is a 16 x 2 synchronous dual-port memory
(SDPM). These new modes offer easier implementa-
tion, faster speeds, denser RAMs, and a dual-port
capability that wasn’t previously offered as an option in
the ATT2Cxx/ATT2Txx families.
If the LUT is configured to operate in the ripple mode, it
cannot be used for basic combinatorial logic or memory
functions. In modes other than the ripple, SSPM, and
SDPM modes, combinations of operating modes are
possible. For example, the LUT can be configured as a
16 x 2 RAM in one HLUT and a five-input combinatorial
logic function in the second HLUT. This can be done by
configuring HLUTA in the MA mode and HLUTB in the
F5B mode (or vice versa).
F4A/F4B Mode—Two Four-Input Functions
Each HLUT can be used to implement two four-input
combinatorial functions, but the total number of inputs
into each HLUT cannot exceed five. The two QLUTs
within each HLUT share three inputs. In HLUTA, the
A1, A2, and A3 inputs are shared by QLUT2 and
QLUT3. Similarly, in HLUTB, the B1, B2, and B3 inputs
are shared by QLUT0 and QLUT1. The four outputs
are F0, F1, F2, and F3. The results can be routed to
the D0, D1, D2, and D3 latch/FF inputs or as an output
of the PFU. The use of the LUT for four functions of up
to four inputs each is given in Figure 4.
F5A/F5B Mode—One Five-Input Variable Function
Each HLUT can be used to implement any five-input
combinatorial function. The input ports are A[4:0] and
B[4:0], and the output ports are F0 and F3. One five or
less input function is input into A[4:0], and the second
five or less input function is input into B[4:0]. The
results are routed to the latch/FF D0 and latch/FF D3
inputs, or as a PFU output. The use of the LUT for two
8
independent functions of up to five inputs is shown in
Figure 5. In this case, the LUT is configured in the F5A
and F5B modes. As a variation, the LUT can do one
function of up to five input variables and two four-input
functions using F5A and F4B modes or F4A and F5B
modes.
A4 A4
HLUTA
A3 A3
QLUT3
A2 A2
F3
A1 A1
A3 A3
A2 A2
QLUT2
A1 A1
F2
A0 A0
B4 B4
HLUTB
B3 B3
QLUT1
B2 B2
F1
B1 B1
B3 B3
B2 B2
QLUT0
B1 B1
F0
B0 B0
5-2753(F).r2
Figure 4. F4 Mode—Four Functions of Four-
Input Variables
WEA
A3
A2
A1
A0
WD3
WD2
WPE
B4
B3
B2
B1
B0
A4
A3 QLUT3
A2
A1 QLUT2
A0
WD3
WD2 c0
B4
B3 QLUT1
B2
B1 QLUT0
B0
HLUTA
F3
F2
HLUTB
F0
5-2845(F).r2
Figure 5. F5 Mode—Two Functions of Five-Input
Variables
Lucent Technologies Inc.







OR2C06A equivalent, schematic
ORCA Series 2 FPGAs
Data Sheet
June 1999
Programmable Logic Cells (continued)
The set/reset operation of the latch/FF is controlled by
two parameters: reset mode and set/reset value. When
the global set/reset (GSRN) or local set/reset (LSR) are
inactive, the storage element operates normally as a
latch or FF. The reset mode is used to select a synchro-
nous or asynchronous LSR operation. If synchronous,
LSR is enabled only if clock enable (CE) is active. For
the Series 2 series, a new option called the LSR prior-
ity allows the synchronous LSR to have priority over the
CE input, thereby setting or resetting the FF indepen-
dent of the state of CE. The clock enable is supported
on FFs, not latches. The clock enable function is imple-
mented by using a two-input multiplexer on the FF
input, with one input being the previous state of the FF
and the other input being the new data applied to the
FF. The select of this two-input multiplexer is clock
enable (CE), which selects either the new data or the
previous state. When CE is inactive, the FF output
does not change when the clock edge arrives.
The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF.
If the local set/reset is not needed, the latch/FF can be
configured to have a data front-end select. Two data
inputs are possible in the front-end select mode, with
the LSR signal used to select which data input is used.
The data input into each latch/FF is from the output of
its associated QLUT F[3:0] or direct from WD[3:0],
bypassing the LUT. In the front-end data select mode,
both signals are available to the latches/FFs.
For PLCs that are in the two outside rows or columns of
the array, the latch/FFs can have two inputs in addition
to the F and WD inputs mentioned above. One input is
from an I/O pad located at the PIC closest to either the
left or right of the given PLC (if the PLC is in the left two
columns or right two columns of the array). The other
input is from an I/O pad located at the closest PIC
either above or below the given PLC (if the PLC is in
the top or the bottom two rows). It should be noted that
both inputs are available for a 2 x 2 array of PLCs in
each corner of the array. For the entire array of PLCs, if
either or both of these inputs is unavailable, the latch/
FF data input can be tied to a logic 0 instead (the
default).
To speed up the interface between signals external to
the FPGA and the latches/FFs, there are direct paths
from latch/FF outputs to the I/O pads. This is done for
each PLC that is adjacent to a PIC.
The latches/FFs can be configured in three modes:
1. Local synchronous set/reset: the input into the PFU’s
LSR port is used to synchronously set or reset each
latch/FF.
2. Local asynchronous set/reset: the input into LSR
asynchronously sets or resets each latch/FF.
3. Latch/FF with front-end select: the data select signal
(actually LSR) selects the input into the latches/FFs
between the LUT output and direct data in.
For all three modes, each latch/FF can be indepen-
dently programmed as either set or reset. Each latch/
FF in the PFU is independently configured to operate
as either a latch or flip-flop. Figure 18 provides the logic
functionality of the front-end select, global set/reset,
and local set/reset operations.
PDINTB
PDINLR
F
WD
LOGIC 0
LSR
GSRN
CD
CE
CE
DQ
S_SET
PDINTB
PDINLR
F
WD
LOGIC 0
S_RESET
CLK
GSRN
LSR
SET RESET
CE PDINTB
PDINLR
D
CE
Q
F
WD
LOGIC 0
LSR CE
CE
DQ
WD
CLK
SET RESET
CLK
SET RESET
GSRN
CD CD
Note: CD = configuration data.
Figure 18. Latch/FF Set/Reset Configurations
5-2839(F).a
16 Lucent Technologies Inc.










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