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PDF ( 数据手册 , 数据表 ) OM4085T

零件编号 OM4085T
描述 Universal LCD driver for low multiplex rates
制造商 NXP Semiconductors
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OM4085T 数据手册, 描述, 功能
INTEGRATED CIRCUITS
DATA SHEET
OM4085
Universal LCD driver for low
multiplex rates
Product specification
Supersedes data of 1996 Nov 14
File under Integrated Circuits, IC12
1997 Feb 25







OM4085T pdf, 数据表
Philips Semiconductors
Universal LCD driver for low multiplex
rates
Product specification
OM4085
handbook, full pagewidth
BP0
BP1
Sn
Sn + 1
VDD
(VDD + VLCD)/2
VLCD
VDD
(VDD + VLCD)/2
VLCD
VDD
VLCD
VDD
VLCD
state 1
state 2
Vop
Vop/2
0
Vop/2
Vop
Vop
Vop/2
0
Vop/2
Vop
Tframe
LCD segments
state 1
state 2
(a) waveforms at driver
At any instant (t):
Vstate 1(t) = VSn(t) VBP0(t)
Von(rms) = Vop10 = 0.791Vop
4
Vstate 2(t) = VSn(t) VBP1(t)
Voff(rms) = Vop2 = 0.354Vop
4
(b) resultant waveforms
at LCD segment
MGG394
1997 Feb 25
Fig.5 Waveforms for 1 : 2 multiplex drive mode with 12 bias: Vop = VDD VLCD.
8







OM4085T equivalent, schematic
Philips Semiconductors
Universal LCD driver for low multiplex
rates
Product specification
OM4085
I2C-BUS DESCRIPTION
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse, set up and hold times must be taken into
account. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.
System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is a ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.11 Bit transfer.
1997 Feb 25
16










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零件编号描述制造商
OM4085Universal LCD driver for low multiplex ratesNXP Semiconductors
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OM4085TUniversal LCD driver for low multiplex ratesNXP Semiconductors
NXP Semiconductors

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