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零件编号 | NE1619 | ||
描述 | Temperature and voltage monitor | ||
制造商 | Philips | ||
LOGO | |||
1 Page
INTEGRATED CIRCUITS
NE1619
HECETA4
Temperature and voltage monitor
Product data sheet
Supersedes data of 2004 May 10
2004 Oct 05
Philips
Semiconductors
Philips Semiconductors
HECETA4 Temperature and voltage monitor
Product data sheet
NE1619
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V (see Note 4); Tamb = 0 °C to +125 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
VDD Supply voltage
IDD Supply current
Standby mode
IDD Supply current
Operating mode
tC
Total monitoring cycle time1
All conversions
TR Temperature resolution
Local and Remote
Tamb = 25 °C
TAI Internal temperature accuracy
Tamb = 0 °C to +120 °C
Tamb = 25 °C
TAE External temperature accuracy
Tamb = 0 °C to +120 °C
IS Remote source current
High level
Low level
2.8 3.3 5.5
– 100 –
– 250 500
– 0.25 0.50
– ±1.0 –
– – ±2.0
– – ±3.0
– – ±3.0
– – ±5.0
– 100 –
– 10 –
Voltage-to-Digital converter (12VIN, 5VIN, 3.3VIN, 2.5VIN, VCCP, VDD)
VUE
Unadjusted error
– – ±2.0
VDNL
Differential non-linearity error
– ±1.0 –
VRIN
VIN input resistance
VPSS
VIN power supply sensitivity
Digital output (SDA, A02)
100 200
– ±1.0
–
–
VOH Output High voltage
VOL Output Low voltage
IOH Output High leakage current
SMB digital input voltages (SDA, SCL)
IOUT = –3.0 mA, VDD = 2.8 V
IOUT = 3.0 mA, VDD = 3.8 V
VOUT = VDD
– – 2.4
0.4 –
–
– 0.1 10.0
VIH Input High voltage
VIL Input Low voltage
Digital input voltages (A0, VID0–4, NT_IN3)
– – 0.6VDD
– – 0.3VDD
VIH Input High voltage
VIL Input Low voltage
Digital input current (all digital inputs)
– – 2.0
0.4 –
–
IIH Input High current
VIN = VDD
–1.0 –
IIL Input Low current
VIN = GND
––
CIN Input capacitance
– 20.0
NOTES:
1. Total monitoring cycle time includes all temperature conversions and all voltage conversions.
2. When A0 is selected as output in NAND-TREE test mode.
3. When D– is selected as input in NAND-TREE test mode.
4. Operating the device at 2.8 V to 5.5 V is allowed, but parameter values in characteristics table are not guaranteed.
–
1.0
–
UNIT
V
µA
µA
sec
°C
°C
°C
°C
°C
µA
µA
%FS
LSB
kΩ
%/V
V
V
µA
V
V
V
V
µA
µA
pF
2004 Oct 05
8
Philips Semiconductors
HECETA4 Temperature and voltage monitor
Product data sheet
NE1619
Printed Circuit Board layout considerations
Care must be taken in PCB layout to minimize noise induced at the
remote temperature sensor inputs, especially in extremely noisy
environments, such as a computer motherboard. Noise induced in
the traces running between the device sensor inputs and the remote
diode can cause temperature conversion errors. Typical sensor
signal levels to the NE1619 is a few microvolts. The following
guidelines are recommended:
1. Place the NE1619 as close as possible to the remote sensor. It
can be from 4 to 8 inches, as long as the worst noise sources
such as clock generator, data and address buses, CRTs are
avoided.
2. Route the D+ and D– lines parallel and close together with
ground guards enclosing them (see Figure 14).
3. Leakage currents due to PC board contamination must be
considered. Error can be introduced by these leakage currents.
4. Use wide traces to reduce inductance and noise pickup. Narrow
traces more readily pickup noise. The minimum width of 10 mil
and space of 10 mil are recommended.
5. Place a bypass capacitor of 100 nF close to the VDD pin and an
input filter capacitor of 2200 pF close to the D+ and D– pins.
6. If the remote sensor is operating in a noisy environment and
located several feet away from the NE1619, a shielded twisted
pair cable is recommended. Make sure the shield of the cable is
connected to the NE1619 ground pin, and leave the shield at the
remote end unconnected. Shield connecting to ground of both
ends could create a ground loop (refer to Figure 15) and defeat
the purpose of the shielded cable. Also, cold soldered joints and
damaged cable could introduce series resistance and reslult in
measurement error. For instance, a 1 Ω resistance can introduce
a change of temperature of about 0.5 °C.
SHIELDED TWISTED PAIR
REMOTE
SENSOR
D+
NE1619
D–
GND
GND
D+
D–
GND
Figure 14. PCB layout for D+ and D–
SL01218
SL02156
Figure 15. Using shielded twisted pair
2004 Oct 05
16
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页数 | 19 页 | ||
下载 | [ NE1619.PDF 数据手册 ] |
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