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PDF ( 数据手册 , 数据表 ) N80C51BH

零件编号 N80C51BH
描述 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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N80C51BH 数据手册, 描述, 功能
80C31BH 80C51BH 87C51
MCS 51
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Automotive
Y Extended Automotive Temperature
Range (b40 C to a125 C Ambient)
Y High Performance CHMOS Process
Y Power Control Modes
Y 4 Kbyte On-Chip ROM EPROM
Y 128 x 8-bit RAM
Y 32 Programmable I O Lines
Y Two 16-Bit Timer Counters
Y 5 Interrupt Sources
Y Quick-Pulse EPROM Programming
Y 2-Level Program Memory Lock EPROM
Y Boolean Processor
Y Programmable Serial Port
Y TTL- and CMOS-Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y IDLE and POWER DOWN Modes
Y ONCE Mode Facilitates System Testing
Y Available in 12 MHz and 16 MHz
Versions
Y Available in PLCC and DIP Packages
(See Packaging Specification Order 231369)
The MCS 51 CHMOS microcontroller products are fabricated on Intel’s reliable CHMOS process and are
functionally compatible with the standard MCS 51 HMOS microcontroller products This technology combines
the high speed and density characteristics of HMOS with the low power attributes of CHMOS This combina-
tion expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set
Like the MCS 51 HMOS microcontroller versions the MCS 51 CHMOS microcontroller products have the
following features 4 Kbytes of EPROM ROM (87C51 80C51BH respectively) 128 bytes of RAM 32 I O lines
two 16-bit timer counters a five-source two-level interrupt structure a full duplex serial port and on-chip
oscillator and clock circuitry In addition the MCS 51 CHMOS microcontroller products exhibit low operating
power along with two software selectable modes of reduced activity for further power reduction Idle and
Power Down
The Idle mode freezes the CPU while allowing the RAM timer counters serial port and interrupt system to
continue functioning The Power Down mode saves the RAM contents but freezes the oscillator causing all
other chip functions to be inoperative
The 87C51 is the EPROM version of the 80C51BH It contains 4 Kbytes of on-chip program memory that can
be electrically programmed and can be erased by exposure to ultraviolet light The 87C51 EPROM array uses
a modified Quick-Pulse Programming algorithm by which the entire 4 Kbyte array can be programmed in about
12 seconds
NOTICE
This datasheet contains information on products in full production Specifications within this datasheet
are subject to change without notice Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
January 1995
Order Number 270419-007







N80C51BH pdf, 数据表
AUTOMOTIVE 80C31BH 80C51BH 87C51
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias b40 C to a125 C
Storage Temperature
b65 C to a150 C
Voltage on EA VPP Pin to VSS
0V to a13 0V
Voltage on Any Other Pin to VSS b0 5V to a6 5V
IOL per I O pin
15 mA
Power Dissipation
1 5W
(Based on package heat transfer limitations not de-
vice power consumption)
Typical Junction Temperature (TJ)
a135 C
(Based upon ambient temperature at a125 C)
Typical Thermal Resistance Junction-to-Ambient
(iJA)
PDIP
75 C W
PLCC
46 C W
NOTICE This is a production data sheet The specifi-
cations are subject to change without notice
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
DC CHARACTERISTICS
(TA e b40 C to a125 C VCC e 5V g10% (5V g20% EPROM Only) VSS e 0V)
Symbol
Parameter
Min
Typ(1)
Max
(87C51 80C51BH)
Unit
Test
Conditions
VIL
VIL1
VIH
VIH1
VOL
VOL1
VOH
VOH1
IIL
ITL
Input Low Voltage (Except EA)
b0 5
Input Low Voltage to EA
0
Input High Voltage (Except XTAL1 RST) 0 2VCCa1 0
Input High Voltage (XTAL1 RST)
0 7 VCCa0 1
Output Low Voltage (Ports 1 2 3)
Output Low Voltage (Port 0 ALE PSEN)
Output High Voltage
(Ports 1 2 3 ALE PSEN)
Output High Voltage (Port 0 in
External Bus Mode)
Logical 0 Input Current (Ports 1 2 3)
24
0 9 VCC
24
0 9 VCC
Logical 1-to-0 transition current
(Ports 1 2 3)
0 2 VCCb0 25
0 2 VCCb0 45
VCCa0 5
VCCa0 5
0 45(7)
0 45(7)
b75
b750
V
V
V
V
V IOL e 1 6 mA(2)
V IOL e 3 2 mA(2)
V IOH e b60 mA
V IOH e b10 mA
V IOH e b800 mA
V IOH e b80 mA(3)
mA VIN e 0 45 V
mA (4)
ILI
ICC
RRST
Input Leakage Current (Port 0)
Power Supply Current
Active Mode 12 MHz (5)
Idle Mode 12 MHz (5)
Power Down Mode
Internal Reset Pulldown Resistor
11 5
13
3
50
g10
25 20
65
100 75
300
mA VIN e VIL or VIH
mA
mA (6)
mA VCC e 2 2V to 5 5V
KX
CIO Pin Capacitance
10 pF
NOTES
1 ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed The
values listed are at room temp 5V
2 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-0 transitions during bus operations In the worst cases (capacitive loading l 100pF) the noise pulse on the ALE pin may
exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt
Trigger STROBE input
3 Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0 9 VCC
specification when the address bits are stabilizing
8







N80C51BH equivalent, schematic
AUTOMOTIVE 80C31BH 80C51BH 87C51
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
FOR PROGRAMMING CONDITIONS SEE FIGURE 11
FOR VERIFICATION CONDITIONS SEE FIGURE 13
270419 – 22
DATASHEET REVISION SUMMARY
The following are the key differences between this datasheet and the -006 version
1 The ‘‘preliminary’’ status was removed and replaced with production status (no label)
2 Trademark was updated
The following are the key differences between the -005 and the -006 version of the datasheet
1 Preliminary notice added to Title page
2 Figure 3 Pin Connections the NC pins are now Reserved pins
3 Figure 3 Pin Connections RST pin is now RESET pin
4 RST pin description is now RESET pin description
5 Figure 4 the capacitor values have been removed
6 CERDIP part reference in the D C Characteristics section has been removed
7 ICC Max characteristics have been corrected to reflect test program conditions
8 TAVIV and TRLDV formulas changed to correlate 12 MHz timings
The following are the key differences between the -004 and the -005 version of this datasheet
1 Removed references to burn-in options in Table 1 and added explanation of burn-in offered Removed
references to commercial temperatures
2 Deleted reference to ‘‘b1’’ designation 16 MHz
3 Differentiated VCC for ROM ROMless and EPROM
The following are the key differences between the -002 and the -003 version of this datasheet
1 Changed the title to 80C31BH 80C51BH 87C51 CHMOS Single-Chip 8-Bit Microcontroller
2 Added the pin count for each package version in Figure 2
3 Removed references to burn-in options in Table 1
4 Added external oscillator start-up design considerations
The following are the key differences between the -002 and the -001 version of the 80C51BH datasheet
1 Maximum IOL per I O pin added
2 Note 7 on Maximum Current Specifications added to DC Characterstics
3 Datasheet Revision Summary added
16










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