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PDF ( 数据手册 , 数据表 ) 93C56

零件编号 93C56
描述 16Kbit/ 8Kbit/ 4Kbit/ 2Kbit/ 1Kbit and 256bit 8-bit or 16-bit wide
制造商 STMicroelectronics
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93C56 数据手册, 描述, 功能
M93C86, M93C76, M93C66
M93C56, M93C46, M93C06
16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide)
MICROWIRE Serial Access EEPROM
FEATURES SUMMARY
s Industry Standard MICROWIRE Bus
s Single Supply Voltage:
– 4.5V to 5.5V for M93Cx6
– 2.5V to 5.5V for M93Cx6-W
– 1.8V to 5.5V for M93Cx6-R
s Dual Organization: by Word (x16) or Byte (x8)
s Programming Instructions that work on: Byte,
Word or Entire Memory
s Self-timed Programming Cycle with Auto-Erase
s Ready/Busy Signal During Programming
s Speed:
– 1MHz Clock Rate, 10ms Write Time (Current
product, identified by process identification
letter F or M)
– 2MHz Clock Rate, 5ms Write Time (New
Product, identified by process identification
letter W)
s Sequential Read Operation
s Enhanced ESD/Latch-Up Behaviour
s More than 1 Million Erase/Write Cycles
s More than 40 Year Data Retention
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DS)
3x3mm body size
TSSOP8 (DW)
169 mil width
M93C06 IS “NOT FOR NEW DESIGN”
The M93C06 is still in production, but is not recom-
mended for new designs. Please refer to AN1571
on how to replace the M93C06 by the M93C46 in
your application.
May 2003
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93C56 pdf, 数据表
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 7. WRAL Sequence
WRITE
ALL
S
D
1 0 0 0 1 Xn X0 Dn
D0
CHECK
STATUS
Q
ADDR
OP
CODE
DATA IN
BUSY
READY
AI00880C
Note: For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6.
Write All
As with the Erase All Memory (ERAL) instruction,
the format of the Write All Memory with same Data
(WRAL) instruction requires that a dummy ad-
dress be provided. As with the Write Data to Mem-
ory (WRITE) instruction, the format of the Write All
Memory with same Data (WRAL) instruction re-
quires that an 8-bit data byte, or 16-bit data word,
be provided. This value is written to all the ad-
dresses of the memory device. The completion of
the cycle can be detected by monitoring the
Ready/Busy line, as described next.
READY/BUSY STATUS
While the Write or Erase cycle is underway, for a
WRITE, ERASE, WRAL or ERAL instruction, the
Busy signal (Q=0) is returned whenever Chip Se-
lect Input (S) is driven High. (Please note, though,
that there is an initial delay, of tSLSH, before this
status information becomes available). In this
state, the M93Cx6 ignores any data on the bus.
When the Write cycle is completed, and Chip Se-
lect Input (S) is driven High, the Ready signal
(Q=1) indicates that the M93Cx6 is ready to re-
ceive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is
brought Low or until a new start bit is decoded.
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note AN394 for details.
8/27







93C56 equivalent, schematic
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 19. AC Characteristics (M93Cx6, temperature range 6 or 3)
Test conditions specified in Table 11 and Table 8
Symbol Alt.
Parameter
Min.3
Max.3
Min.4
Max.4
fC fSK Clock Frequency
D.C. 1 D.C. 2
tSLCH
Chip Select Low to Clock High
250
50
tSHCH
Chip Select Set-up Time
tCSS
M93C46, M93C56, M93C66
Chip Select Set-up time
M93C76, M93C86
50
100
50
50
tSLSH2
tCS Chip Select Low to Chip Select High
250
200
tCHCL1
tSKH Clock High Time
250 200
tCLCH1
tSKL Clock Low Time
250 200
tDVCH
tDIS Data In Set-up Time
100 50
tCHDX
tDIH Data In Hold Time
100 50
tCLSH
tSKS Clock Set-up Time (relative to S)
100
50
tCLSL
tCSH Chip Select Hold Time
00
tSHQV
tSV Chip Select to Ready/Busy Status
400 200
tSLQZ
tDF Chip Select Low to Output Hi-Z
200 100
tCHQL
tPD0 Delay to Output Low
400 200
tCHQV
tPD1 Delay to Output Valid
400 200
tW tWP Erase/Write Cycle time
10 5
Note: 1. tCHCL + tCLCH 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: identified by Process Identification letter W.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
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