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PDF ( 数据手册 , 数据表 ) NS486SXL

零件编号 NS486SXL
描述 Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems
制造商 National
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NS486SXL 数据手册, 描述, 功能
ADVANCE INFORMATION
December 1997
NS486SXL
Optimized 32-Bit 486-Class Controller with On-Chip
Peripherals for Embedded Systems
General Description
The NS486SXL is a highly integrated embedded system
controller incorporating an Intel486-class 32-bit processor
along with all of the necessary System Service Elements,
implementing a true “system on a chip.” It is ideally suited for
a wide variety of applications running in a segmented
protect-mode environment. The NS486SXL is the second
member of the NS486 family.
Features
n 100% compatible with VxWorks, VRTX, QNX
Neutrino, pSOS +®, and other popular real-time
executives and operating system kernels
n Intel486 instruction set compatible (protected mode only)
with optimized performance
n Operation at 25 MHz with 5V supply
n Low cost 132-pin PQFP package
n Industry standard interrupt controller, timers, and real
time clock
n Protected WATCHDOGtimer
n Optimized DRAM Controller (supports two banks, up to
8 Mbytes each)
n Up to nine versatile, programmable chip selects
n Up to eight external interrupts directly supported, and
additional interrupt expansion through an external PIC
interface
n Glueless interface to ISA-type peripherals
n Arbitration support for auxiliary processor
n Support for External Bus Masters, allowing them to
access DRAM and on-chip Peripherals
n MICROWIRE/Access.bus synchronous serial
interfaces
n UART with IrDA v1.0 (Infrared Data Association) port
n Reconfigurable I/O: Up to 28 I/O pins can be used as
general purpose bidirectional I/O lines
n Flexible, programmable, multilevel power saving modes
maximize power savings
n Programming model compatible with the NS486SXF
where possible
Block Diagram NS486SXL Single-Chip Embedded Controller
MICROWIRE, NS486and WATCHDOGare trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Intel486is a trademaek of Intel Corporation.
pSOS +is a trademark of Integrated Systems, Inc.
VRTXis a registered trademark of Microtec Research, Inc.
PowerPack® is a registered trademark of Microtek International.
QNXis a registered trademark of QNX Software Systems, Inc.
VxWorksis a registered trademark of Wind River Systems, Inc.
© 1998 National Semiconductor Corporation DS100121
DS100121-1
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NS486SXL pdf, 数据表
2.0 SXL Pin Description Tables
TABLE 1. Bus Interface Unit Pins
Symbol
SA[31:0]
SD[15:0]
ALS
SBHE
D/C
Pins
81, 82, 83, 84,
85, 86, 87, 88,
89, 90, 91, 92,
93, 94, 96, 97,
99, 100, 101,
102, 103, 104,
105, 106, 107,
108, 109, 111,
112, 114, 115,
116
119, 120, 122,
123, 125, 126,
127, 128, 130,
132, 1, 3, 4, 5,
6, 7
117
76
48
Type
I/O
Function
System Address bus. These input-output signals carry the latched address for the
current access. DRAM accesses multiplex the row and column addresses for the
DRAMs on the SA[12:1] pins. Note: An incompatibility was introduced into the
first silicon of the ’SXL. During Interrupt Acknowledge cycles, the internal
master interrupt controller’s cascade line signals, CAS[2:0], are driven onto
SA[31:29], respectively. Formerly the CAS[2:0] signals were driven onto
SA[25:23] in the ’SXF. The SA[31:0] pins are inputs when an External Master is
in control of the bus, except when the ’SXL does a DRAM access for the External
Master (see MAE, below).
I/O System Data bus: This bi-directional data bus provides the data path for all
memory and I/O accesses. During transfers with 8-bit devices, the upper data
byte is not used (SD[15:8]).
O Address Latch Strobe. This pulse is produced by a variety of bus related
activities. The ALS strobe will go low every time a bus cycle is initiated by the
internal CPU, even if the cycle is killed due to an internal instruction-cache “hit.”
The strobe will also go active for each DRAM access, and each eight-bit access
for 16-to-8 bit translations by the Bus Interface Unit (BIU). The strobe will be
produced for internal and external I/O accesses as well. Finally, the strobe will go
active low during External Bus Master accesses so the BIU can indicate to the
internal CPU that it should “snoop” an access to possibly invalidate cache entries.
I/O Byte High Enable. This active-low signal is driven when the address is asserted
by the CPU. External 16-bit devices should use this signal to help them determine
that a data byte is to be transferred on the upper byte of the System Data bus
(SD[15:8]). Eight-bit devices should ignore this signal. The ’SXL bus interface will
automatically translate 16-bit requests from the internal CPU into two eight bit
accesses for external memories and peripherals that do not assert CS16.
This pin becomes an input when an External Master is in control of the bus. An
External Master should drive SBHE appropriately according to the type of access
it is requesting, and be prepared to handle 8-bit devices if a 16-bit access is
attempted and no CS16 is produced. The ’SXL bus interface will automatically
translate 16-bit accesses from the External Master into two eight-bit accesses for
internal peripherals. The ’SXL will also respond with CS16 on accesses to internal
peripherals and accesses to any programmed Chip Select that has the “force
16-bit” feature enabled.
SBHE Truth Table
SBHE SA[0] Function
0 0 The bus master is requesting a 16-bit transfer
1 0 An 8-bit transfer on the low-byte is requested
0 1 An 8-bit transfer on the high-byte is requested
1 1 Illegal case
O Data/Control This output is provided to indicate what kind of access the ’SXL
internal CPU is making. During the time that an External Master controls the bus,
D/C will be high, indicating Data accesses. D/C is high for I/O and Memory
accesses that are considered “data” by executing instructions. D/C is low for code
fetches from memory, interrupt acknowledge cycles and Halt/Special bus events.
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NS486SXL equivalent, schematic
Real Time Clock (RTCX1/CLK)
Symbol
Parameter
VIH
VIL
VBAT
IBAT
RTCX1 Input High Voltage
RTCX1 Input Low Voltage
Battery Voltage
Battery Current
Note 9: RTCX2 is the output.
Note 10: Lithium Battery.
(Note 9)
(Note 10)
Conditions
Timer
Symbol
VOH
VOL
Parameter
Output High Voltage
Output Low Voltage
Conditions
IOH = −6 mA on: T0, T1
IOL = 6 mA on: T0, T1
General Purpose Chip Selects
Symbol
VOH
VOL
Parameter
Output High Voltage
Output Low Voltage
Conditions
IOH = −6 mA on: CS5–0
IOL = 6 mA on: CS5–0
Interrupt Controller
Symbol
VOH
VOL
Parameter
Output High Voltage
Output Low Voltage
Conditions
IOH = −12 mA on: INTA
IOL = 12 mA on: INTA
3-Wire I/O (and Access.bus)
Symbol
VOH
VOL
Parameter
Output High Voltage
Output Low Voltage
Conditions
IOH = −12 mA on: SO, SI, SCLK
IOL = 12 mA on: SO, SI, SCLK
General AC Specifications
AC TEST CONDITIONS
Test Circuit for Output Tests
Min Max Unit
2.0
0.4 V
2.4 V
Min Max Unit
2.4 V
0.4 V
Min Max Unit
2.4 V
0.4 V
Min Max Unit
2.4 V
0.4 V
Min Max Unit
2.4 V
0.4 V
Note 1: S1 = VCC for tPZL, anf tPLZ measurements.
S1 = GND for tPZH, and tPHZ measurements
S1 = Open for push pull outputs
Note 2: RL = 1.1k
Note 3: CL includes scope and jig capacitance
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DS100121-5
16










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