DataSheet8.cn


PDF ( 数据手册 , 数据表 ) NS32FX161-15

零件编号 NS32FX161-15
描述 Advanced Imaging/Communication Signal Processors
制造商 National
LOGO National LOGO 


1 Page

No Preview Available !

NS32FX161-15 数据手册, 描述, 功能
February 1992
NS32FX161-15 NS32FX161-20 NS32FX164-20
NS32FX164-25 NS32FV16-20 NS32FV16-25
Advanced Imaging Communication Signal Processors
General Description
The NS32FX164 the NS32FV16 and the NS32FX161 are
high-performance 32-bit members of the Series 32000
EPTM family of National’s Embedded System ProcessorsTM
specifically optimized for CCITT Group 2 and Group 3 Fac-
simile Applications Data Modems Voice Mail Systems La-
ser Printers or any combination of the above
Unless specified otherwise any reference to the
NS32FX164 in this document applies to the NS32FV16 and
the NS32FX161 as well
The NS32FX164 can perform all the computations and con-
trol functions required for a stand-alone Fax system a PC
add-in Fax Voice Data Modem card or a Laser Fax sys-
tem
It also meets the performance requirements to implement
14400 9600 and 7200 bps modems complying with CCITT
V 17 V 29 and V 27 standards The NS32FV16 supports
V 29 and V 27 standards as well as voice The NS32FX161
supports V 29 and V 27 standards
The NS32FX164 provides a 16 Mbyte Linear external ad-
dress space and a 16-bit external data bus
The CPU core which is the same as that of the NS32CG16
incorporates a 32-bit ALU and instruction pipeline and an
8-byte prefetch queue
Also integrated on-chip with the CPU are a DSP Module
(DSPM) and a 4K-byte RAM Array (2K in the NS32FV16 and
NS32FX161) The DSPM is a complete processing unit ca-
pable of autonomous operation parallel to the CPU core
operation The DSPM executes programs stored in an inter-
nal on-chip Random Access Memory (RAM) and manipu-
lates data stored either in the internal RAM or in an external
off-chip memory To maximize utilization of hardware re-
sources the DSPM contains a pipelined DSP-oriented data-
path and a control logic that implements a set of DSP vec-
tor commands
The NS32FX164 capabilities can be expanded by using an
external floating point unit (FPU) which directly interfaces to
the NS32FX164 using the slave protocol The CPU-FPU
cluster features high speed execution of the floating-point
instructions
The NS32FX164 highly-efficient architecture combined with
the NS32CG16 graphics instructions and the high-perform-
ance vector operation capability makes the device the ideal
choice for PostscriptTM and Fax applications
Features
Y Software compatible with the Series 32000 EP
processors
Y Designed around the CPU core of the NS32CG16
Y Pin compatible with the NS32FX16
Y 32-bit architecture and implementation
Y On-chip DSP Module for high-speed DSP operations
Y Special support for graphics applications
18 graphics instructions
Binary compression expansion capability for font
storage using RLL encoding
Pattern magnification
Interface to an external BITBLT processing units for
fast color BITBLT operations
Y 4K-byte on-chip RAM array (2K in NS32FV16 and
NS32FX161)
Y On-chip clock generator
Y Floating-point support via the NS32081 or NS32181
Y Optimal interface to large memory arrays via the
NS32CG821 and the DP84xx family of DRAM
controllers
Y Power save mode
Y High-speed CMOS technology
Y 68-pin PLCC package
Block Diagram
FIGURE 1-1 CPU Block Diagram
Series 32000 is a registered trademark of National Semiconductor Corporation
EPTM and Embedded System ProcessorsTM are trademarks of National Semiconductor Corporation
PostscriptTM is a trademark of Adobe Systems Inc
C1995 National Semiconductor Corporation TL EE11267
TL EE 11267 – 1
RRD-B30M115 Printed in U S A







NS32FX161-15 pdf, 数据表
2 0 Architectural Description (Continued)
2 1 2 Address Registers
The seven address registers are used by the processor to
implement specific address functions Except for the MOD
register that is 16 bits wide all the others are 32 bits A
description of the address registers follows
PC Program Counter The PC register is a pointer to the
first byte of the instruction currently being executed The PC
is used to reference memory in the program section
SP0 SP1 Stack Pointers The SP0 register points to the
lowest address of the last item stored on the INTERRUPT
STACK This stack is normally used only by the operating
system It is used primarily for storing temporary data and
holding return information for operating system subroutines
and interrupt and trap service routines The SP1 register
points to the lowest address of the last item stored on the
USER STACK This stack is used by normal user programs
to hold temporary data and subroutine return information
When a reference is made to the selected Stack Pointer
(see PSR S-bit) the terms ‘‘SP Register’’ or ‘‘SP’’ are used
SP refers to either SP0 or SP1 depending on the setting of
the S bit in the PSR register If the S bit in the PSR is 0 SP
refers to SP0 If the S bit in the PSR is 1 then SP refers to
SP1
Stacks in the Series 32000 architecture grow downward in
memory A Push operation pre-decrements the Stack Point-
er by the operand length A Pop operation post-increments
the Stack Pointer by the operand length
FP Frame Pointer The FP register is used by a procedure
to access parameters and local variables on the stack The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction
The frame pointer holds the address in memory occupied by
the old contents of the frame pointer
SB Static Base The SB register points to the global vari-
ables of a software module This register is used to support
relocatable global variables for software modules The SB
register holds the lowest address in memory occupied by
the global variables of a module
INTBASE Interrupt Base The INTBASE register holds
the address of the dispatch table for interrupts and traps
(Section 3 2 1)
MOD Module The MOD register holds the address of the
module descriptor of the currently executing software mod-
ule The MOD register is 16 bits long therefore the module
table must be contained within the first 64 kbytes of memo-
ry
2 1 3 Processor Status Register
The Processor Status Register (PSR) holds status informa-
tion for the microprocessor
The PSR is sixteen bits long divided into two eight-bit
halves The low order eight bits are accessible to all pro-
grams but the high order eight bits are accessible only to
programs executing in Supervisor Mode
15 8 7
0
B I PSUNZ F J K L TC
FIGURE 2-2 Processor Status Register (PSR)
C The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction It can be used with
the ADDC and SUBC instructions to perform multiple-
precision integer arithmetic calculations It may have a
setting of 0 (no carry or borrow) or 1 (carry or borrow)
T The T bit causes program tracing If this bit is set to 1 a
TRC trap is executed after every instruction (Section
3 3 1)
L The L bit is altered by comparison instructions In a com-
parison instruction the L bit is set to ‘‘1’’ if the second
operand is less than the first operand when both oper-
ands are interpreted as unsigned integers Otherwise it
is set to ‘‘0’’ In Floating-Point comparisons this bit is
always cleared
K Reserved for use by the CPU
J Reserved for use by the CPU
F The F bit is a general condition flag which is altered by
many instructions (e g integer arithmetic instructions
use it to indicate overflow)
Z The Z bit is altered by comparison instructions In a com-
parison instruction the Z bit is set to ‘‘1’’ if the second
operand is equal to the first operand otherwise it is set
to ‘‘0’’
N The N bit is altered by comparison instructions In a
comparison instruction the N bit is set to ‘‘1’’ if the sec-
ond operand is less than the first operand when both
operands are interpreted as signed integers Otherwise
it is set to ‘‘0’’
U If the U bit is ‘‘1’’ no privileged instructions may be exe-
cuted If the U bit is ‘‘0’’ then all instructions may be
executed When Ue0 the processor is said to be in Su-
pervisor Mode when Ue1 the processor is said to be in
User Mode A User Mode program is restricted from exe-
cuting certain instructions and accessing certain regis-
ters which could interfere with the operating system For
example a User Mode program is prevented from
changing the setting of the flag used to indicate its own
privilege mode A Supervisor Mode program is assumed
to be a trusted part of the operating system hence it has
no such restrictions
S The S bit specifies whether the SP0 register or SP1 reg-
ister is used as the Stack Pointer The bit is automatical-
ly cleared on interrupts and traps It may have a setting
of 0 (use the SP0 register) or 1 (use the SP1 register)
P The P bit prevents a TRC trap from occurring more than
once for an instruction (Section 3 3 1) It may have a
setting of 0 (no trace pending) or 1 (trace pending)
I If Ie1 then all interrupts will be accepted If Ie0 only
the NMI interrupt is accepted Trap enables are not af-
fected by this bit
8







NS32FX161-15 equivalent, schematic
2 0 Architectural Description (Continued)
2 4 3 Instruction Set Summary
Table 2-2 presents a brief description of the NS32FX164
instruction set The Format column refers to the Instruction
Format tables (Appendix A) The Instruction column gives
the instruction as coded in assembly language and the De-
scription column provides a short description of the function
provided by that instruction Further details of the exact op-
erations performed by each instruction may be found in the
Series 32000 Instruction Set Reference Manual and the
NS32CG16 Printer Display Processor Programmer’s Refer-
ence
Notations
ieInteger length suffix B e Byte
We Word
D e Double Word
feFloating Point length suffix FeStandard Floating
LeLong Floating
geneGeneral operand Any addressing mode can be speci-
fied
shorteA 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings)
immeImplied immediate operand An 8-bit value appended
after any addressing extensions
dispeDisplacement (addressing constant) 8 16 or 32 bits
All three lengths legal
regeAny General Purpose Register R0 – R7
aregeAny Processor Register SP SB FP INTBASE
MOD PSR US (bottom 8 PSR bits)
condeAny condition code encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings)
MOVES
Format
Operation
TABLE 2-2 NS32FX164 Instruction Set Summary
Operands
Description
4 MOVi
gen gen
Move a value
2 MOVQi short gen Extend and move a signed 4-bit constant
7
MOVMi
gen gen disp
Move multiple disp bytes (1 to 16)
7
MOVZBW
gen gen
Move with zero extension
7
MOVZiD
gen gen
Move with zero extension
7
MOVXBW
gen gen
Move with sign extension
7
MOVXiD
gen gen
Move with sign extension
4 ADDR
gen gen
Move effective address
INTEGER ARITHMETIC
Format
Operation
Operands
Description
4 ADDi
2 ADDQi
4 ADDCi
4 SUBi
4 SUBCi
6 NEGi
6 ABSi
7 MULi
7 QUOi
7 REMi
7 DIVi
7 MODi
7 MEIi
7 DEIi
gen gen
short gen
gen gen
gen gen
gen gen
gen gen
gen gen
gen gen
gen gen
gen gen
gen gen
gen gen
gen gen
gen gen
Add
Add signed 4-bit constant
Add with carry
Subtract
Subtract with carry (borrow)
Negate (2’s complement)
Take absolute value
Multiply
Divide rounding toward zero
Remainder from QUO
Divide rounding down
Remainder from DIV (Modulus)
Multiply to extended integer
Divide extended integer
PACKED DECIMAL (BCD) ARITHMETIC
Format
Operation
Operands
Description
6 ADDPi
6 SUBPi
gen gen
gen gen
Add packed
Subtract packed
16










页数 30 页
下载[ NS32FX161-15.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
NS32FX161-15Advanced Imaging/Communication Signal ProcessorsNational
National

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap