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PDF ( 数据手册 , 数据表 ) NM93C46

零件编号 NM93C46
描述 1024-Bit Serial CMOS EEPROM (MICROWIRE Synchronous Bus)
制造商 Fairchild
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NM93C46 数据手册, 描述, 功能
February 2000
NM93C46
1024-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
NM93C46 is a 1024-bit CMOS non-volatile EEPROM organized
as 64 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
There are 7 instructions implemented on the NM93C46 for various
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.
“LZ” and “L” versions of NM93C46 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space consid-
erations.
Features
I Wide VCC 2.7V - 5.5V
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
DATA IN/OUT REGISTER
16 BITS
DO DATA OUT BUFFER
VCC
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
VSS
© 2000 Fairchild Semiconductor International
NM93C46 Rev. E
1
www.fairchildsemi.com







NM93C46 pdf, 数据表
Timing Diagrams
;SYNCHRONOUS DATA TIMING
;
CS ;;
;;; ;; ;; ;tSKS tCSS
tSKH
tSKL
;
; ;tCSH
SK ; ; ;; ;; ;
; ;;;;; ; ;tDIS tDIH
;;
;;
DI
;;;;;; ;;;;;;;; ;Valid
Input
Valid
Input
;;;;;;;;;;;;;;;;;;;
;;;;;; ;;;t;PD;;;; ;tDH;;;tP;D ;;;;;;;;;;;;;;tDF;;
;;;;;;;;;;;;;; ;;;;;; ;;;;;;;; ;DO (Data Read)
Valid
Output
Valid
Output
; tSV;;;;;;; ;;;;;; ;;;;;;;; ;tDF
;;;;;;;;;DO (Status Read)
Valid Status
;
NORMAL READ CYCLE (READ)
CS
tCS
SK
1 1 0 A5 A4
A1
DI
Start Opcode
Address
Bit Bits(2)
Bits(6)
High - Z
DO
93C46:
Address bits pattern -> User defined
A0 ;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
0 D15
;;;D1 D0
Dummy
Bit
;;;
WRITE ENABLE CYCLE (WEN)
CS
tCS
SK
1 0 0 A5 A4
A1 A0
DI
Start Opcode
Address
Bit Bits(2)
Bits(6)
High - Z
DO
93C46:
Address bits pattern -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
NM93C46 Rev. E
8 www.fairchildsemi.com














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