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PDF ( 数据手册 , 数据表 ) 8840

零件编号 8840
描述 In-System Programmable SuperBIG High Density PLD
制造商 Lattice Semiconductor
LOGO Lattice Semiconductor LOGO 


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8840 数据手册, 描述, 功能
ispLSI® 8840
In-System Programmable
SuperBIG™ High Density PLD
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 5V Power Supply
— 45,000 PLD Gates/840 Macrocells
— Up to 312 I/O Pins Supporting 3.3V/5V I/O
— 1152 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 110 MHz Maximum Operating Frequency
tpd = 8.5 ns Propagation Delay
— TTL Compatible Inputs and 3.3V/5V Outputs
— PCI Compatible Inputs, Outputs and Speed Grades
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
5V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply for Output Drivers
Supports 5V or 3.3V Outputs
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
Global Routing Plane
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
12
I/O
Big Fast Megablock 4
12
I/O
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
Boundary
Scan
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
8840 block
ispLSI 8000 Family Description
The ispLSI 8000 Family of Register-Intensive, SuperBIG
In-System Programmable Logic Devices is based on Big
Fast Megablocks of 120 registered macrocells and a
Global Routing Plane (GRP) structure interconnecting
the Big Fast Megablocks. Each Big Fast Megablock
contains 120 registered macrocells arranged in six groups
of 20, a group of 20 being referred to as a Generic Logic
Block, or GLB. Within the Big Fast Megablock, a Big Fast
Megablock Routing Pool (BRP) interconnects the six
GLBs to each other and to 24 Big Fast Megablock I/O
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
January 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
8840_07
1







8840 pdf, 数据表
Specifications ispLSI 8840
Output Control Organization
In addition to the data input and output to the I/O cells,
each I/O cell can have up to six different I/O cell control
signals. In addition to the internal OE control, the five
control signals for each I/O cell consist of pin OE control,
clock enable, clock input, asynchronous preset and asyn-
chronous reset. All of the I/O control signals can be driven
either from the dedicated external input pins or from the
internal control bus.
The output enable of each I/O cell can be driven by 21
different sources 16 from the output control bus, four
from the Global OE pins and one from the Test OE pin.
The Global OE signals and Test OE signal are driven
from the dedicated external control input pins.
The 16-bit wide output control buses are organized in four
different quadrants as shown in Figure 5. Since each
GLB is capable of generating the output control signals,
each of the output control bus signals can be driven from
a unique GLB. The 42 GLBs can generate a total of 42
unique I/O control signals. Referring to Figure 2, the GLB
generates its output control signal from control product
term (PT81).
Figure 5 also illustrates how the quadrant clocks are
routed to the appropriate quadrant I/O cells.
Figure 5. Output Control Bus and Quadrant Organization
Quadrant 0, 16-Bit Wide Output Control Bus
(I/O B0-B6 <0-11>, QIOCLK0)
GLB
Generated
Output
Control
(see Figure 2)
From PT81
Quadrant 2, 16-Bit Wide Output Control Bus
(I/O B0-B6 <12-23>, QIOCLK2)
8
OE Bus.eps







8840 equivalent, schematic
Specifications ispLSI 8840
ispLSI 8840 Timing Model
I/O
pad
Input
pad
Input Buffer and I/O Cell Register
#69, tbcom
#70, tbreg
I/O register delays
#25, tobp
Output path
#71, tgcom
#72, tgreg
#26, tibp
Input path
Input buffer
#27, tiolat
delays
#23, tidcom
#24, tidreg
#28, tioco
#29, tiosu
#30, tioh
BFM Routing Pool #61, tbfmi #67, tbfmg
#64, tbfmm
#31, tiorst
#32, tiosuce
#33, tiohce
GLB/
Macrocell
Local feedback
#54, tfloc
Toggle feedback
Output routing
z
Output
buffer
delays
#34, todreg
#35, todcom
#36, todz
Global control
delay
AND array
#39,
tandhs
#40,
tandlp
PTSA
#41, t1pt
#53,
tftog
#42, t4ptcom
#43, t4ptreg
#44, tptsa
PT Mcell controls
#55, tpck
#56, tpcken
#57, tsck
#58, tscken
#59, tprst
Mcell register
#45, tmbp
#46, tmlat
#47, tmco
#48, tmsu
#49, tmh
#50, tmrst
#51, tmsuce
#52, tmbce
PT I/O control bus
Bus direct
#60, trdir
Global
Routing
Plane
#62, tgrpi
#63, tgrpiz
#65, tgrpm
#66, tgrpmz
#68, tgrpb
#78, tgck
#79, tgcken
#80, tgiock
#81, tgiocken
#82, tqck
#83, tgoe
#84, ttoe
#85, tgmrst
#86, tgiorst
#73, tpiock
#74, tpiocken
#75, tpoe
#76, tpiorst
#77, tpioz
8K_Model.eps
Output
slew rate
adders
#37, tslf
#38, tsls
I/O
pad
16










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