DataSheet8.cn


PDF ( 数据手册 , 数据表 ) 85015013A

零件编号 85015013A
描述 CMOS Serial Controller Interface
制造商 Intersil Corporation
LOGO Intersil Corporation LOGO 


1 Page

No Preview Available !

85015013A 数据手册, 描述, 功能
82C52
March 1997
CMOS Serial Controller Interface
Features
• Single Chip UART/BRG
• DC to 16MHz (1M Baud) Operation
• Crystal or External Clock Input
• On-Chip Baud Rate Generator - 72 Selectable Baud
Rates
• Interrupt Mode with Mask Capability
• Microprocessor Bus Oriented Interface
• 80C86 Compatible
• Single +5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
• Modem Interface
• Line Break Generation and Detection
• Operating Temperature Range:
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
1M BAUD
CP82C52
IP82C52
CS82C52
IS82C52
CD82C52
ID82C52
MD82C52/B
8501501XA
MR82C52/B
85015013A
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
Pinouts
82C52 (PDIP, CERDIP)
TOP VIEW
RD 1
WR 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
A0 11
A1 12
IX 13
OX 14
28 CSO
27 VCC
26 DR
25 SDI
24 INTR
23 RST
22 TBRE
21 CO
20 RTS
19 DTR
18 DSR
17 CTS
16 GND
15 SDO
82C52 (PLCC, CLCC)
TOP VIEW
4 3 2 1 28 27 26
D2 5
25 SDI
D3 6
24 INTR
D4 7
23 RST
D5 8
D6 9
22 TBRE
21 CO
D7 10
20 RTS
A0 11
19 DTR
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-1
File Number 2950.1







85015013A pdf, 数据表
82C52
Bit 0, which corresponds to D0 at the data bus, is always the
first serial data bit transmitted. Provision is made for the
transmitter parity to be the same or different from the
receiver. The TBRE output pin and flag (USR register) reflect
the status of the TBR. The TC flag (USR register) indicates
when both TBR and TR are empty.
82C52 Interrupt Structure
The 82C52 has provisions for software masking of interrupts
generated for the INTR output pin. Two control bits in the
MCR register, MIEN and INTEN, control modem status inter-
rupts and overall 82C52 interrupts respectively. Figure 9
illustrates the logical control function provided by these sig-
nals.
The modem status inputs (DSR and CTS) will trigger the
edge detection circuitry with any change of status. Reading
the MSR register will clear the detect circuit but has no effect
on the status bits themselves. These status bits always
reflect the state of the input pins regardless of the mask con-
trol signals. Note that the state (high or low) of the status bits
are inverted versions of the actual input pins.
The edge detection circuits for the USR register signals will
trigger only for a positive edge (true assertion) of these sta-
tus bits. Reading the USR register not only clears the edge
detect circuit but also clears (sets to 0) all of the status bits.
The output pins associated with these status bits are not
affected by reading the USR register.
A hardware reset of the 82C52 sets the TC status bit in the
USR. When interrupts are subsequently enabled an interrupt
can occur due to the fact that the positive edge detection cir-
cuitry in the interrupt logic has detected the setting of the TC
bit. If this interrupt is not desired the USR should be read
prior to enabling interrupts. This action resets the positive
edge detection circuitry in the interrupt control logic (Figure 9).
NOTE: For USR and MSR, the setting of status bits is inhibited
during status register READ operations. If a status condition is gen-
erated during a READ operation, the status bit is not set until the trail-
ing edge of the RD pulse.
If the bit was already set at the time of the READ operation, and the
same status condition occurs, that status bit will be cleared at the
trailing edge of the RD pulse instead of being set again.
RBRK, TC
OE, FE, PE
(USR)
POS.
EDGE
DETECT
RD (USR)
DSR, CTS
(MSR)
RD (MSR)
POS. OR
NEG.
EDGE
DETECT
INTEN
(MCR)
MIEN
(MCR)
FIGURE 9. 82C52 INTERRUPT STRUCTURE
INTR
PIN 24
Software Reset
A software reset of the 82C52 is a useful method for
returning to a completely known state without exercising a
complete system reset. Such a reset would consist of writing
to the UCR, BRSR and MCR registers. The USR and RBR
registers should be read prior to enabling interrupts in order
to clear out any residual data or status bits which may be
invalid for subsequent operation.
Crystal Operation
The 82C52 crystal oscillator circuitry is designed to operate
with a fundamental mode, parallel resonant crystal. This cir-
cuit is the same one used in the Intersil 82C84A clock gener-
ator/driver. To summarize, Table 3 and Figure 10 show the
required crystal parameters and crystal circuit configuration
respectively.
When using an external clock source, the IX input is driven
and the OX output is left open. Power consumption when
using an external clock is typically 50% of that required when
using a crystal. This is due to the sinusoidal nature of the
drive circuitry when using a crystal.
TABLE 3.
PARAMETER
TYPICAL CRYSTAL
SPECIFICATION
Frequency
1.0 to 16MHz
Type of Operation
Parallel Resonant, Fundamental Mode
Load Capacitance (CL) 20 or 32pF (Typ)
RSERIES(Max)
100(f = 16MHz, CL = 32pF)
200(f = 16MHz, CL = 20pF)
GND
C1 (NOTE)
C2 (NOTE)
IX
82C52
OX
NOTE: C1 = C2 = 20pF For CL = 20pF
C1 = C2 = 47pF For CL = 32pF
FIGURE 10.
82C52 - 80C86 Interfacing
The following example (Figure 11) shows the interface for an
82C52 in an 80C86 system.
Use of the Intersil CMOS Interrupt Controller (82C59A) is
optional and necessary only if an interrupt driven system is
desired.
By using the Intersil CMOS 82C84A clock generator, the
system can be built with a single crystal providing both the
processor clock and the clock for the 82C52. The 82C52 has
special divider circuitry which is designed to supply industry
standard baud rates with a 2.4576MHz input frequency.
Using a 15MHz crystal as shown, results in less than a 2%
frequency error which is adequate for many applications. For
more precise baud rate requirements, a 14.7456MHz crystal
will drive the 80C86 at 4.9MHz and provide the 82C52 with
the standard baud rate input frequency of 2.4576MHz. If
baud rates above 156Kbaud are desired, the OSC output
can be used instead of the PCLK (÷6) output for asynchro-
nous baud rates up to 1Mbaud.
5-8







85015013A equivalent, schematic
82C52
UART Timing Characterization (Continued)
11 12 13 14 15 16 1/I 2/I 3/I
CO(BRG)
SDI
RD
(25)
TDRH
DR NOTE 1
INTR NOTE 2
LAST STOP BIT
RBR
(26)
TRLDL
(21)
TIHF
START BIT / IDLE
USR
(23)
TRLIL
FIGURE 19. RECEIVE TIMING
WR
RTS/DTR
MCR
(27)
TWHO
RD MSR
DSR/CTS
(22)
TIHM
(23)
TRLIL
INTR NOTE 3
FIGURE 20. OTHER TIMING
NOTES:
1. DR bit D7 in USR is updated each time DR changes state. TDRH always from trailing edge of 11th CO(BRG) in last Stop bit.
2. INTR on receive flags OE, FE, PE, and RBRK: INTEN enabled; Respective USR bits updated at this time regardless of interrupt config-
uration.
- INT on OE, FE, PE, RBRK occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit. To avoid OE, RD(RBR) must go low
by the trailing edge of the 8th CO(BRG) in the last Stop bit.
3. INTR on MS: INTEN and MIEN enabled; USR bit D4(MS) is updated at this time regardless of INTEN/MIEN.
- INTR on MS occurs whenever CTS or DSR input changes state.
5-16










页数 19 页
下载[ 85015013A.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
85015013ACMOS Serial Controller InterfaceIntersil Corporation
Intersil Corporation

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap