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PDF ( 数据手册 , 数据表 ) 84069012A

零件编号 84069012A
描述 CMOS Bus Controller
制造商 Intersil Corporation
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84069012A 数据手册, 描述, 功能
82C88
March 1997
CMOS Bus Controller
Features
Description
• Compatible with Bipolar 8288
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz)
- 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 8089
• Provides Advanced Commands for Multi-Master
Busses
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)
• Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C88 is a high performance CMOS Bus Con-
troller manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). The 82C88 provides the control
and command timing signals for 80C86, 80C88, 8086, 8088,
8089, 80186, and 80188 based systems. The high output
drive capability of the 82C88 eliminates the need for addi-
tional bus drivers.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
Ordering Information
PART NUMBER
CP82C88
CP82C88-10
IP82C88
CS82C88
IS82C88
CD82C88
ID82C88
MD82C88/B
8406901RA
MR82C88/B
84069012A
PACKAGE
20 Ld PDIP
20 Ld
PLCC
20 Ld
CERDIP
SMD#
20 Pad
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG.
NO.
E20.3
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
20 LEAD PDIP, CERDIP
TOP VIEW
IOB 1
CLK 2
S1 3
DT/ R 4
ALE 5
AEN 6
MRDC 7
AMWC 8
MWTC 9
GND 10
20 VCC
19 S0
18 S2
17 MCE/PDEN
16 DEN
15 CEN
14 INTA
13 IORC
12 AIOWC
11 IOWC
20 LEAD PLCC, CLCC
TOP VIEW
3 2 1 20 19
DT/ R 4
ALE 5
AEN 6
18 S2
17 MCE/PDEN
16 DEN
MRDC 7
15 CEN
AMWC 8
14 INTA
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-333
File Number 2979.1







84069012A pdf, 数据表
Timing Waveforms (Note 3) (Continued)
82C88
CEN
AEN
DEN
PDEN
TAEVNV (22)
TCEVNV (23)
FIGURE 2. DEN, PDEN QUALIFICATION TIMING
AEN
OUTPUT
COMMAND
1.5V
TAELCH (19)
TAELCV
(21)
VOH
1.5V
TAEHCZ (20)
0.5V VOH
CEN
TCELRH
(24)
TCELRH (24)
CEN MUST BE LOW OR INVALID PRIOR TO T2 TO PREVENT THE COMMAND FROM BEING GENERATED.
FIGURE 3. ADDRESS ENABLE (AEN) TIMING (THREE-STATE ENABLE/DISABLE)
NOTES:
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
4-340














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