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PDF ( 数据手册 , 数据表 ) 8406602QA

零件编号 8406602QA
描述 CMOS Programmable Peripheral Interface
制造商 Intersil Corporation
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8406602QA 数据手册, 描述, 功能
82C55A
June 1998
CMOS Programmable
Peripheral Interface
Features
Description
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Ordering Information
PART NUMBERS
TEMPERATURE PKG.
5MHz
8MHz PACKAGE
RANGE
NO.
CP82C55A-5
IP82C55A-5
CP82C55A
0oC to 70oC
IP82C55A 40 Ld PDIP -40oC to 85oC
E40.6
E40.6
CS82C55A-5
IS82C55A-5
CS82C55A
0oC to 70oC
IS82C55A 44 Ld PLCC -40oC to 85oC
N44.65
N44.65
CD82C55A-5 CD82C55A
ID82C55A-5
ID82C55A
40 Ld
CERDIP
MD82C55A-5/B MD82C55A/B
0oC to 70oC
-40oC to 85oC
-55oC to 125oC
F40.6
F40.6
F40.6
8406601QA 8406602QA SMD#
F40.6
MR82C55A-5/B
MR82C55A/B
44 Pad
CLCC
-55oC to 125oC J44.A
8406601XA 8406602XA SMD#
J44.A
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Pinouts
82C55A (DIP)
TOP VIEW
82C55A (CLCC)
TOP VIEW
PA3 1
PA2 2
PA1 3
PA0 4
RD 5
CS 6
GND 7
A1 8
A0 9
PC7 10
PC6 11
PC5 12
PC4 13
PC0 14
PC1 15
PC2 16
PC3 17
PB0 18
PB1 19
PB2 20
40 PA4
39 PA5
38 PA6
37 PA7
36 WR
35 RESET
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 VCC
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
6 5 4 3 2 1 44 43 42 41 40
GND 7
NC 8
A1 9
A0 10
PC7 11
PC6 12
PC5 13
PC4 14
PC0 15
PC1 16
PC2 17
39 NC
38 RESET
37 D0
36 D1
35 D2
34 D3
33 D4
32 D5
31 D6
30 D7
29 NC
18 19 20 21 22 23 24 25 26 27 28
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
82C55A (PLCC)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 1920 21 22 23 24 25 26 27 28
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 2969.2







8406602QA pdf, 数据表
82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #12
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 0 0
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
CONTROL WORD #14
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 1 0
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
CONTROL WORD #13
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 0 1
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 1 1
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
Operating Modes
Mode 1 - (Strobed Input/Output). This functional configura-
tion provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “hand shaking”
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these “hand shaking” signals.
Mode 1 Basic Function Definitions:
• Two Groups (Group A and Group B)
• Each group contains one 8-bit port and one 4-bit
control/data port
• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
• The 4-bit port is used for control and status of the 8-bit
port.
Input Control Signal Definition
(Figures 6 and 7)
STB (Strobe Input)
A “low” on this input loads data into the input latch.
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledg-
ment. IBF is set by STB input being low and is reset by the
rising edge of the RD input.
MODE 1 (PORT A)
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0
PC6, PC7
1 = INPUT
0 = OUTPUT
RD
PA7-PA0
INTE
A
PC4
PC5
8
STBA
IBFA
PC3
PC6, PC7
INTRA
2
I/O
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 11
MODE 1 (PORT B)
PB7-PB0
INTE
B
PC2
PC1
8
STBB
IBFB
PC0
INTRB
RD
FIGURE 6. MODE 1 INPUT
8







8406602QA equivalent, schematic
82C55A
INTERRUPT
REQUEST
PC3
MODE 2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
82C55A
PC4
PC5
PC7
PC6
PC2
PC1
PC0
D0
D1
D2
D3
FLOPPY DISK
CONTROLLER
D4 AND DRIVE
D5
D6
D7
DATA STB
ACK (IN)
DATA READY
ACK (OUT)
TRACK “0” SENSOR
SYNC READY
INDEX
MODE 0
(OUTPUT)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
ENGAGE HEAD
FORWARD/REV.
READ ENABLE
WRITE ENABLE
DISC SELECT
ENABLE CRC
TEST
BUSY LT
FIGURE 23. BASIC FLOPPY DISC INTERFACE
INTERRUPT
REQUEST
PC3
MODE 1
(INPUT)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PC6
82C55A
MODE 0
(INPUT)
PC0
PC1
PC2
R0
R1
R2
R3
B LEVEL
PAPER
R4 TAPE
R5 READER
R6
R7
STB
ACK
STOP/GO
MACHINE TOOL
START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID
MODE 0
(OUTPUT)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CHANGE TOOL
LEFT/RIGHT
UP/DOWN
HOR. STEP STROBE
VERT. STEP STROBE
SLEW/STEP
FLUID ENABLE
EMERGENCY STOP
FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE
16










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