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PDF ( 数据手册 , 数据表 ) NM25C020

零件编号 NM25C020
描述 2K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
制造商 Fairchild
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NM25C020 数据手册, 描述, 功能
March 1999
NM25C020
2K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
Features
The NM25C020 is a 2048-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C020 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C020 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
s 2.1 MHz clock rate @ 2.7V to 5.5V
s 2048 bits organized as 256 x 8
s Multiple chips on the same 3-wire bus with separate chip
select lines
s Self-timed programming cycle
s Simultaneous programming of 1 to 4 bytes at a time
s Status register can be polled during programming to monitor
READY/BUSY
s Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
s Block write protect feature to protect against accidental
writes
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
CS
HOLD
SCK
SI
Instruction
Register
Instruction
Decoder
Control Logic
and Clock
Generators
VCC
VSS
WP
Address
Counter/
Register
Decoder
1 of 256
Program
Enable
VPP
EEPROM Array
2048 Bits
(256 x 8)
High Voltage
Generator
and
Program
Timer
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
DS012400-1
© 1999 Fairchild Semiconductor Corporation
NM25C020 Rev. D.1
1
www.fairchildsemi.com







NM25C020 pdf, 数据表
Functional Description (Continued)
FIGURE 10. Write Sequence
The WRSR command requires the following sequence. The CS
line is pulled low to select the device and then the WRSR op-code
is transmitted on the SI line followed by the data to be pro-
CS grammed. See Figure 12.
SCK
SI D2
D1
D0
SO
DS012400-12
The READY/BUSY status of the device can be determined by
FIGURE 12. Write Status Register
CS
SI
WRSR
SR Data
Op-Code xxxxBP1BP0xx
SO
DS012400-14
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRITE cycle is still in progress and Bit 0 =
0 indicates that the WRITE cycle has ended. During the WRITE
programming cycle (Bit 0 = 1) only the READ STATUS REGIS-
TER instruction is enabled.
The NM25C020 is capable of a 4 byte PAGE WRITE operation.
After receipt of each byte of data the two low order address bits are
internally incremented by one. The seven high order bits of the
address will remain constant. If the master should transmit more
Note that the first four bits are don’t care bits followed by BP1 and
BP0 then two additional don’t care bits. Programming will start
after the CS pin is forced back to a high level. As in the WRITE
instruction the LOW to HIGH transition of the CS pin must occur
during the SCK low time immediately after clocking in the last don’t
care bit. See Figure 13.
FIGURE 13. Start WRSR Condition
than 4 bytes of data, the address counter will “roll over,” and the
previously loaded data will be reloaded. See Figure 11.
CS
FIGURE 11. 4 Byte Page Write
CS
SI
Write
Byte
Op-Code Addr (n)
Data
(n)
Data Data Data
(n + 1) (n + 2) (n + 3)
SO
SCK
SI BP0
SO
DS012400-15
DS012400-13 The READY/BUSY status of the device can be determined by
At the completion of a WRITE cycle the device is automati-
cally returned to the write disable state.
If the device is not WRITE enabled, the device will ignore the
WRITE instruction and return to the standby state when CS is
forced high. A new CS falling edge is required to re-initialize the
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRSR cycle is still in progress and Bit 0 =
0 indicates that the WRSR cycle has ended.
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
serial communication.
WRITE STATUS REGISTER (WRSR): The WRITE STATUS
REGISTER (WRSR) instruction is used to program the non-
volatile status register Bits 2 and 3 (BP0 and BP1). The WRITE
PROTECT (WP) pin must be held high and two separate instruc-
tions must be executed. The chip must first be write enabled via
the WRITE ENABLE instruction and then a WRSR instruction
must be executed.
NM25C020 Rev. D.1
8 www.fairchildsemi.com














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