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PDF ( 数据手册 , 数据表 ) NM24W08

零件编号 NM24W08
描述 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
制造商 Fairchild
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NM24W08 数据手册, 描述, 功能
PRELIMINARY
March 1999
NM24Wxx
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
General Description
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-
tively, of CMOS non-volatile electrically erasable memory. These
devices conform to all specifications in the IIC 2-wire protocol and
are designed to minimize device pin count, and simplify PC board
layout requirements.
The entire ememory can be disabled (Write Protected) by con-
necting the WP pin to VCC. The memory then becomes unalterable
unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by Fairchild's family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Features
s Hardware Write Protect for entire memory
s Low Power CMOS
200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s IIC Compatible interface
— Provides bidirectional data transfer protocol
s Sixteen byte page write mode
— Minimizes total write time per byte
s Self timed write cycle
— Typical write cycle time of 6ms
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
s Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
SDA
SCL
A2
A1
A0
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
XDEC
16/
32/
64/
128/
0/1/2/3
4
4
E2PROM
ARRAY
16
YDEC
Device Address Bits
DIN
8
CK
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
NM24Wxx Rev. C.2
1
DS500074-1
www.fairchildsemi.com







NM24W08 pdf, 数据表
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (see Figure 4). This
is fixed as 1010 for all EEPROM devices.
Slave Addresses (Figure 4)
Device Type
Identifier
Device
Address
1 010
NM24W02
Device Type
Identifier
A2 A1 A0 R/W (LSB)
Device
Address
1 0 1 0 A2 A1 A0 R/W (LSB)
NM24W04
Device Type
Identifier
Page
Block Address
Device
Address
1 010
NM24W08
Device Type
Identifier
A2 A1 A0 R/W (LSB)
Page
Block Address
All Standard IIC protocol EEPROMs use an internal protocol that
defines a PAGE BLOCK size of 2K bits (for Byte addresses 00
through FF). Therefore, address bits A0, A1, or A2 (if designated
'P') are used to access a PAGE BLOCK in conjuction with the Byte
address used to access any individual data byte.
Refer to the following table for Slave Address string details:
Device A0 A1 A2 Page
Blks
Page Block
Addresses
NM24W02 A A A 1 (2K)
NM24W04 P A A 2 (4K)
(None)
01
NM24W08 P P A 4 (8K)
00 01 10 11
NM24W16 P P P 8 (16K) 000 001 010 011 100
101 110 111
Note: A: Refers to a hardware configured Device Address pin.
P: Refers to an internal PAGE BLOCK memory segment
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
A simple review: After the NM24Wxx recognizes the start condi-
tion, the devices interfaced to the IIC bus wait for a slave address
to be transmitted over the SDA line. If the transmitted slave
address matches an address of one of the devices, the designated
slave pulls the line LOW with an acknowledge signal and awaits
further transmissions.
1 0 1 0 A2 A1 A0 R/W (LSB)
NM24W16
Page
Block Address
DS500074-11
NM24Wxx Rev. C.2
8 www.fairchildsemi.com














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