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PDF ( 数据手册 , 数据表 ) NM24C32

零件编号 NM24C32
描述 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
制造商 Fairchild
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NM24C32 数据手册, 描述, 功能
PRELIMINARY
March 1999
NM24C32
32K-Bit Extended 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description:
The NM24C32 devices are 32,768 bits of CMOS nonvolatile
electrically erasable memory. These devices offer the designer
different low voltage and low power options, and they conform to
all specifications in the Extended IIC 2-wire protocol. Furthermore,
they are designed to minimize device pin count and simplify PC
board layout requirements.
The upper half of the memory can be disabled (Write Protection)
by connecting the WP pin to VCC. This section of memory then
becomes ROM.
This communication protocol uses CLOCK (SCL) and DATA I/O
(SDA) lines to synchronously clock data between the master (for
example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Features:
s Extended operating voltage 2.7V – 5.5V
s 400 KHz clock frequency (F) at 2.7V - 5.5V
s 200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s IIC compatible interface
– Provides bidirectional data transfer protocol
s 32 byte page write mode
– Minimizes total write time per byte
s Self timed write cycle
Typical write cycle time of 6ms
s Hardware write protect for upper block
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin SO, 8-pin DIP
s Low VCC programming lockout (3.8V - on Standard VCC
devices only).
Block Diagram
VCC
WP
SDA
WRITE
LOCKOUT
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SCL
A2
A1
A0
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
XDEC
E2PROM
ARRAY
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
NM24C32 Rev. C.2
1
DS500073-1
www.fairchildsemi.com







NM24C32 pdf, 数据表
DEVICE ADDRESSING
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all EEPROM devices.
The next three bits identifies the device address. Address from
000 to 111 are acceptable thus allowing up to eight devices to be
connected to the IIC bus.
The last bit of the slave address defines whether a write or read
condition is requested by the master. A "1" indicates that a READ
operation is to be executed and a "0" initiates the WRITE mode.
A simple review: After the NM24C32xxx recognizes the start
condition, the devices interfaced to the IIC bus waits for a slave
address to be transmitted over the SDA line. If the transitted slave
address matches an address of one of the devices, the designated
slave pulls the line LOW with an acknowledge. signal and awaits
further transmissions.
Write Operations
BYTE WRITE
For a WRITE operation, two additional address bytes, with 12
active bits, are required after the SLAVE acknowledge to address
the full memory array. The first byte indicates the high-order byte
of the word address. Only the four least signicant bits can be
changed, the other bits are pre-assigned the value "0". Following
the acknowledgement from the first word address, the next byte
indicates the low-order byte of the word address. Upon receipt of
the word address, the NM24C32xxx responds with another ac-
knowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
NM24C32xxx begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress, the device's
inputs are disabled and the device will not respond to any requests
from the master. Refer to Figure 5 for the address, acknowledge
and data transfer sequence.
PAGE WRITE
The NM24C32xxx is capable of thirty-two byte page write opera-
tion. It is initiated in the same manner as the byte write operation;
but instead of termination the write cycle after the first data word
is transfered, the master can transmit up to thirty-one more words.
After the receipt of each word, the device responds with an
acknowledge.
After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is ac-
cepted. If the master should transmit more than thirty-two words
prior to generating the stop condition, the address counter will "roll
over" and the previous written data will be overwritten. As with the
byte write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address, acknowl-
edge and data transfer sequence.
Acknowledge Polling
Once the stop condition is isssued to indicate the end of the host's
write operation, the NM24C32xxx initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the NM24C32xxx is still busy with the write operation, no ACK
will be returned. If the device has completed the write operation,
an ACK will be returned and the host can then proceed with the
next read or write operation.
Byte Write (Figure 5)
S
T
Bus Activity: A
Master R
T
SLAVE
ADDRESS
SDA Line 1 0 1 0
Bus Activity
WORD
ADDRESS (1)
WORD
ADDRESS (0)
0000
A
C
K
A
C
K
A
C
K
DATA
S
T
O
P
A
C
K
DS500073-8
NM24C32 Rev. C.2
8 www.fairchildsemi.com














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