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PDF ( 数据手册 , 数据表 ) 83C055

零件编号 83C055
描述 Microcontrollers for TV and video MTV
制造商 NXP Semiconductors
LOGO NXP Semiconductors LOGO 


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83C055 数据手册, 描述, 功能
INTEGRATED CIRCUITS
DATA SHEET
83C145; 83C845
83C055; 87C055
Microcontrollers for TV and video
(MTV)
Product specification
File under Integrated Circuits, IC20
1996 Mar 22







83C055 pdf, 数据表
Philips Semiconductors
Microcontrollers for TV and video (MTV)
Product specification
83C145; 83C845
83C055; 87C055
7 DESCRIPTION OF STANDARD FUNCTIONS
For a description of the standard functions please refer to
the “Data Handbook IC20; Section 2: 80C51 Technical
Description” .
8 INPUT/OUTPUT (I/O)
The I/O structure of the 83C055 is similar to the standard
I/O structure in the 80C51, except for the points described
in Table 5.
9 DESCRIPTION OF DERIVATIVE FUNCTIONS
9.1 General description
Although the 83C055 is specifically referred to throughout
this data sheet, the information applies to all the devices.
The differences to 80C51 features and the derivative
functions are described in the following Sections and
Chapters.
Figure 1 shows the block diagram of the 83C055.
9.1.1 NOT IMPLEMENTED FUNCTIONS
Standard functions to the 80C51 that are not implemented
in the 83C055:
As Data and Program Memory are not externally
expandable on the 83C055, the ALE, EA, and
PSEN signals are not implemented.
Idle mode.
Power-down mode.
9.1.2 INTERRUPT FACILITIES DIFFERENCES
The interrupt facilities of the 83C055 differ from those of
the 80C51 as follows:
The IP register is not used, and the IE register (address
A8H) is similar to that on the 80C51;see Table 36.
The VSYNC input used by the OSD facility can generate
an interrupt. The active polarity of the pulse is
programmable (see Section 13.7); interrupt occurs at
the leading edge of the pulse.
Since there is no serial port, there are no interrupts nor
control bits relating to this interrupt. The interrupts and
their vector addresses are shown in Table 3.
External Interrupt 1 is modified so that an interrupt is
generated when the input switches are in either direction
(on the 80C51, there is a programmable choice between
interrupt on a negative edge or a LOW level on INT1).
This facility allows for software pulse-width
measurement handling of a remote control.
Table 3 Program Memory address
EVENT
Reset
External INT0
Timer 0
External INT1
Timer 1
VSync Start
PROGRAM MEMORY ADDRESS
000H
003H
00BH
013H
01BH
023H
9.1.3 PCON REGISTER DIFFERENCE
The PCON register format is shown in Table 4. Bits GF1
and GF0 are general purpose flag bits.
Table 4 PCON Register format (address 87H)
7654321
− − − − GF1 GF0
0
9.1.4 I/O PORTS DIFFERENCES
Table 5 I/O ports differences
I/O
Port 0
Port 1
Port 2
Port 3
STANDARD 80C51
83C055
external memory expansion
8-bit open-drain bidirectional port; and includes:
alternative use for PWM outputs
8-bit general purpose quasi-bidirectional
4-bit open-drain port, and includes alternative uses
for analog inputs and a PWM output
quasi-bidirectional and can be used for external
memory expansion
open-drain and general purpose
quasi-bidirectional; all eight bits have alternate uses 3 port bits have some of the same alternative uses
as on the 80C51 but not necessarily on the same
pins; 5 pins are open-drain and general purpose
1996 Mar 22
8







83C055 equivalent, schematic
Philips Semiconductors
Microcontrollers for TV and video (MTV)
Product specification
83C145; 83C845
83C055; 87C055
13 ON SCREEN DISPLAY (OSD)
Figure 7 shows the OSD block diagram. It shows the CPU
writing into the 128 × 10 display RAM, which is dual-ported
to allow the CPU to write into it at any time, including when
it is being read out by the OSD logic. The 10-bit wide data
coming out of the display RAM is used to access the
appropriate character in the Character Generator memory
(6-bits) and to specify character and display control
functions (4-bits).
Timing for the OSD is controlled by the HSYNC, VSYNC,
and dot clock input VCLK1.
13.1 OSD features
The 83C055 features an advanced OSD function with
some unique features as described in Sections 13.1.1 to
13.1.10.
13.1.1 USER-DEFINABLE DISPLAY FORMAT
The OSD does not restrict the user to a fixed number of
lines with a fixed number of characters per line:
Using a fixed number of lines restricts the generation of
displays that can be differentiated from others that use
the same chip and places limits on screen content.
Using a fixed number of characters per line wastes
display RAM if a line has less than the full number of
displayable characters (it has to be padded with
non-visible characters).
The OSD on the 83C055 defines a control character:
New Line, that has the same function as a Carriage
Return and Line Feed.
When the OSD circuitry fetches this character from display
RAM it stops displaying further characters, waits for the
next horizontal scan line, and starts displaying the next
character in display RAM after the New Line character was
received.
The number of lines is thus up to the user, within the limits
of the display and memory, as are the number of
characters per line. This allows far better control of the
appearance of the OSD.
13.1.3 DUAL-PORTED DISPLAY RAM
The OSD has a true display RAM instead of a character
line buffer. This display RAM is dual-ported to allow
updating the display RAM at any time instead of having to
wait for a vertical retrace.
Vertical Sync (VSYNC) interrupts are supported if
flicker-free updates are required.
13.1.4 PROGRAMMABLE CHARACTER SIZE
Normal characters are displayed as 18 × 14 bit maps.
In an interlaced display:
– 2 fields are displayed so that one actually sees a
36 × 14 pixel size character.
– The part has a double height and width mode which
displays 36 × 28 pixel size bit maps per field.
For use in non-interlaced systems, the part has a double
height mode so that the displayed characters have the
same pixel size (36 × 14) as on an interlaced display.
13.1.5 CHARACTER SHADOWING
When characters are displayed overlaid on a background
of base video, a black border around the characters makes
them highly legible. This feature is called shadowing. The
83C055 has 8 shadowing modes to allow the user to select
various partial shadow modes as well as full surround
shadow; see Fig.8 and Table 28.
13.1.6 PROGRAMMABLE POLARITIES
Inputs to and outputs from the OSD can be programmed
to be recognized as active LOW or HIGH. In conjunction
with the 12 V outputs, this allows direct interfacing to most
video signal processing circuits.
13.1.7 CHARACTER GENERATOR MEMORY IN EPROM
On the 87C055, the Character Generator memory is in
EPROM. This feature allows quick and inexpensive font
development and refinement against the alternative of
creating a masked ROM version to see how the final fonts
will appear.
13.1.2 COLOURS SELECTABLE BY CHARACTER
Characters can be displayed on a background of the base
video or a programmable background colour.
The background colour is selectable by word and the
choice of background (base video/user programmed
colour) by character.
13.1.8 HSYNC LOCKED DOT CLOCK OSCILLATOR
The 83C055 is designed to use an LC oscillator circuit that
is started at the trailing edge of HSYNC and stopped at its
leading edge. In practice, this gives a highly consistent
delay from HSYNC to oscillator start and is stable from
scan line to scan line so that no left margin effects are
seen.
1996 Mar 22
16










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