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PDF ( 数据手册 , 数据表 ) 82378ZB

零件编号 82378ZB
描述 SYSTEM I/O APIC(SIO.A) AND
制造商 Intel Corporation
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82378ZB 数据手册, 描述, 功能
E
82378ZB SYSTEM I/O (SIO) AND
82379AB SYSTEM I/O APIC (SIO.A)
Provides the Bridge Between the PCI
Bus and ISA Bus
100% PCI and ISA Compatible
PCI and ISA Master/Slave Interface
Directly Drives 10 PCI Loads and 6
ISA Slots
PCI at 25 MHz and 33 MHz
ISA from 6 MHz to 8.33 MHz
Enhanced DMA Functions
Scatter/Gather (S/G) (82378ZB)
Fast DMA Type A, B and F (82378ZB)
Compatible DMA Transfers
32-bit Addressability(82378ZB)
27-bit Addressability(82379AB)
Seven Independently Programmable
Channels
Functionality of Two 82C37A DMA
Controllers
Data Buffers to Improve Performance
8-Byte DMA/ISA Master Line Buffer
32-bit Posted Memory Write Buffer to
ISA
Integrated 16-bit BIOS Timer
Non-Maskable Interrupts (NMI)
PCI System Errors
ISA Parity Errors
Arbitration for ISA Devices
ISA Masters
DMA and Refresh
Four Dedicated PCI Interrupts
Level Sensitive
Mapped to Any Unused Interrupt
Arbitration for PCI Devices
Six PCI Masters Supported
Fixed, Rotating, or a Combination
Utility Bus (X-Bus) Peripheral Support
Provides Chip Select Decode
Controls Lower X-Bus Data Byte
Transceiver
Functionality of One 82C54 Timer
System Timer
Refresh Request
Speaker Tone Output
Functionality of Two 82C59 Interrupt
Controllers
14 Interrupts Supported
Edge/Level Selectable Interrupts
I/O APIC (Advanced Programmable
Interrupt Controller (82379AB)
Support for Multi-Processor Systems
System Power Management (Intel SMM
Support)
Programmable System Management
Interrupt (SMI)Hardware Events,
Software Events, EXTSMI#
Programmable CPU Clock Control
(STPCLK#)
Fast-On/Off Mode
208-Pin QFP Package
The 82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A) components are PCI-to-ISA Bus Bridge
devices. These devices integrate many of the common I/O functions found in today's ISA-based PC systemsa
seven channel DMA controller, two 82C59 interrupt controllers, an 8254 timer/counter, a BIOS timer, Intel SMM
power management support, and logic for NMI generation. In addition, the SIO and SIO.A each support a total of
six PCI Masters, and four PCI Interrupts. Decode is provided for peripheral devices such as the flash BIOS, real
time clock, keyboard/mouse controller, floppy controller, two serial ports, one parallel port, and IDE hard disk
drive.
For both the SIO and SIO.A, each DMA channel supports compatibility transfers. The SIO also supports types
A, B, and F transfers and scatter/gather. In addtion to the standard ISA-compatible interrupt controller that is in
both the SIO and SIO.A, the SIO.A contains an Advance Programmable Interrupt Controller (IO APIC) for use in
multi-processing systems.
This document describes both the 82378ZB (SIO) and 82379AB (SIO.A) components. Unshaded areas describe
the 82378ZB. Shaded areas, like this one, describe differences between the 82379AB and 82378ZB.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of
any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor
variations to this specification known as errata. Other brands and names are the property of their respective owners.
© INTEL CORPORATION 1996
March 1996
Order Number: 290571-001







82378ZB pdf, 数据表
82378ZB (SIO) AND 82379AB (SIO.A)
E
8







82378ZB equivalent, schematic
82378ZB (SIO) AND 82379AB (SIO.A)
E
Signal Name Type
Description
MEMREQ# t/s/o
MEMORY REQUEST: If the SIO/SIO.A is configured in Guaranteed Access Time
(GAT) Mode, MEMREQ# will be asserted when an ISA master or DMA is
requesting the ISA Bus (along with FLSHREQ#) to indicate that the SIO/SIO.A
requires ownership of the main memory. MEMREQ# is tri-stated from the leading
edge of PCIRST#. MEMREQ# remains tri-stated until driven by the SIO/SIO.A.
After PCIRST, MEMREQ# is driven inactive asynchronously from PCIRST#
inactive. The SIO/SIO.A asserts FLSHREQ# concurrently with asserting
MEMREQ#.
FLSHREQ# MEMREQ# Meaning
FLSHREQ# t/s/o
1 1 Idle
0 1 Flush buffers pointing towards PCI to
avoid ISA deadlock
1 0 82378ZB. Reserved
82379AB. GAT enabled or disabled: For buffer
coherency in APIC systems, the buffers
pointing to main memory must be flushed
and disabled for the duration of assertion.
0 0 GAT mode. Guarantee PCI Bus immediate
access to main memory (this may or may
not require the PCI-to-main memory
buffers to be flushed first depending on
the number of buffers).
FLUSH REQUEST: FLSHREQ# is generated by the SIO/SIO.A to command all of
the system's posted write buffers pointing towards the PCI Bus to be flushed. This is
required before granting the ISA Bus to an ISA master or the DMA. FLSHREQ# is
tri-stated from the leading edge of PCIRST#. FLSHREQ# remains tri-stated until
driven by the SIO/SIO.A. After PCIRST, FLSHREQ# is driven inactive
asynchronously from PCIRST# inactive.
MEMACK# I
MEMORY ACKNOWLEDGE: MEMACK# is the response handshake that indicates
to the SIO/SIO.A that the function requested over the MEMREQ# and/or
FLSHREQ# signals has been completed. In GAT mode (MEMREQ# and
FLSHREQ# asserted), the main memory bus is dedicated to the PCI Bus and the
system's posted write buffers pointing towards the PCI Bus have been flushed and
are disabled. In non-GAT mode (FLSHREQ# asserted alone), this means the
system's posted write buffers have been flushed and are disabled. In either case,
the SIO/SIO.A can now grant the ISA Bus to the requester.
2.3. Address Decoder Signal
Signal Name Type
Description
MEMCS#
O
MEMORY CHIP SELECT. MEMCS# is a programmable address decode signal
provided to a Host CPU bridge. A CPU bridge can use MEMCS# to forward a PCI
cycle to main memory behind the bridge. MEMCS# is driven one PCI clock after
FRAME# is sampled active (address phase) and is valid for one clock cycle before
going inactive. MEMCS# is high upon reset.
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