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PDF ( 数据手册 , 数据表 ) 82375EB

零件编号 82375EB
描述 PCI-EISA BRIDGE (PCEB)
制造商 Intel Corporation
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82375EB 数据手册, 描述, 功能
82375EB 82375SB PCI-EISA BRIDGE (PCEB)
Y Provides the Bridge Between the PCI
Local Bus and EISA Bus
Y 100% PCI and EISA Compatible
PCI and EISA Master Slave Interface
Directly Drives 10 PCI Loads and 8
EISA Slots
Supports PCI from 25 to 33 MHz
Y Data Buffers Improve Performance
Four 32-bit PCI-to-EISA Posted Write
Buffers
Four 16-byte EISA-to-PCI Read Write
Line Buffers
EISA-to-PCI Read Prefetch
EISA-to-PCI and PCI-to-EISA Write
Posting
Y Data Buffer Management Ensures Data
Coherency
Flush Posted Write Buffers
Flush or Invalidate Line Buffers
System-Wide Data Buffer Coherency
Control
Y Burst Transfers on both the PCI and
EISA Buses
Y 32-Bit Data Paths
Y Integrated EISA Data Swap Buffers
Y Arbitration for PCI Devices
Supports Six PCI Masters
Fixed Rotating or a Combination of
the Two
Supports External PCI Arbiter and
Arbiter Cascading
Y PCI and EISA Address Decoding and
Mapping
Positive Decode of Main Memory
Areas (MEMCS Generation)
Four Programmable PCI Memory
Space Regions
Four Programmable PCI I O Space
Regions
Y Programmable Main Memory Address
Decoding
Main Memory Sizes up to
512 MBytes
Access Attributes for 15 Memory
Segments in First 1 MByte of Main
Memory
Programmable Main Memory Hole
Y Integrated 16-bit BIOS Timer
Y Only Available as Part of a Supported
Kit
The 82375EB SB PCI-EISA Bridge (PCEB) provides the master slave functions on both the PCI Local Bus
and the EISA Bus Functioning as a bridge between the PCI and EISA buses the PCEB provides the address
and data paths bus controls and bus protocol translation for PCI-to-EISA and EISA-to-PCI transfers Exten-
sive data buffering in both directions increases system performance by maximizing PCI and EISA Bus efficien-
cy and allowing concurrency on the two buses The PCEB’s buffer management mechanism ensures data
coherency The PCEB integrates central bus control functions including a programmable bus arbiter for the
PCI Bus and EISA data swap buffers for the EISA Bus Integrated system functions include PCI parity genera-
tion system error reporting and programmable PCI and EISA memory and I O address space mapping and
decoding The PCEB also contains a BIOS Timer that can be used to implement timing loops The PCEB is
intended to be used with the EISA System Component (ESC) to provide an EISA I O subsystem interface
This document describes both the 82375EB and 82375SB components Unshaded areas describe the
82375EB Shaded areas like this one describe the 82375SB operations that differ from the 82375EB
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1996
Order Number 290477-004







82375EB pdf, 数据表
82375EB SB
1 0 ARCHITECTURAL OVERVIEW
The PCI-EISA bridge chip set provides an I O subsystem core for the next generation of high-performance
personal computers (e g those based on the Intel486TM or Pentium processors) System designers can take
advantage of the power of the PCI local bus while maintaining access to the large base of EISA and ISA
expansion cards and corresponding software applications Extensive buffering and buffer management within
the PCI-EISA bridge ensures maximum efficiency in both bus environments
The chip set consists of two components the 82375EB PCI-EISA Bridge (PCEB) and the 82374EB EISA
System Component (ESC) These components work in tandem to provide an EISA I O subsystem interface for
personal computer platforms based on the PCI standard This section provides an overview of the PCI and
EISA Bus hierarchy followed by an overview of the PCEB and ESC components
Bus Hierarchy Concurrent Operations
Figure 1 shows a block diagram of a typical system using the PCI-EISA Bridge chip set The system contains
three levels of buses structured in the following hierarchy
 Host Bus as the execution bus
 PCI Bus as a primary I O bus
 EISA Bus as a secondary I O bus
PCI Bus
The PCI Bus has been defined to address the growing industry needs for a standardized local bus that is not
directly dependent on the speed and the size of the processor bus New generations of personal computer
system software such as WindowsTM and Win-NTTM with sophisticated graphical interfaces multi-tasking and
multi-threading bring new requirements that traditional PC I O architectures can not satisfy In addition to the
higher bandwidth reliability and robustness of the I O subsystem are becoming increasingly important The
PCI environment addresses these needs and provides an upgrade path for the future PCI features include
 Processor independent
 Multiplexed burst mode operation
 Synchronous up to 33 MHz
 120 MByte sec usable throughput (132 MByte sec peak) for 32-bit data path
 240 MByte sec usable throughput (264 MByte sec peak) for 64-bit data path
 Optional 64-bit data path with operations that are transparent with the 32-bit data path
 Low latency random access (60 ns write access latency to slaves from a master parked on the bus)
 Capable of full concurrency with processor memory subsystem
 Full multi-master capability allowing any PCI master peer-to-peer access to any PCI slave
 Hidden (overlapped) central arbitration
 Low pin count for cost effective component packaging (multiplexed address data)
 Address and data parity
 Three physical address spaces memory I O and configuration
 Comprehensive support for autoconfiguration through a defined set of standard configuration functions
8







82375EB equivalent, schematic
82375EB SB
Pin Name
C BE 3 0
FRAME
TRDY
IRDY
STOP
PLOCK
Type
Description
t s BUS COMMAND AND BYTE ENABLES The command and byte enable signals are
multiplexed on the same PCI pins During the address phase of a transaction
C BE 3 0 define the bus command for bus command definitions During the data
phase C BE 3 0 are used as Byte Enables The Byte Enables determine which
byte lanes carry meaningful data C BE 0 applies to byte 0 and C BE 3 to byte
3 C BE 3 0 are not used for address decoding
The PCEB drives C BE 3 0 as an initiator of a PCI Bus cycle and monitors
C BE 3 0 as a target
When PCIRST is asserted the PCEB drives C BE 3 0 to keep them from
floating In addition the PCEB acts as the central resource responsible for driving the
C BE 3 0 signals when no device owns the PCI Bus and the bus is idle
sts
FRAME FRAME is driven by the current initiator to indicate the beginning and
duration of an access FRAME is asserted to indicate that a bus transaction is
beginning During a transaction data transfers continue while FRAME is asserted
When FRAME is negated the transaction is in the final data phase FRAME is an
input when the PCEB is the target FRAME is an output when the PCEB is the
initiator During reset this signal is tri-stated
sts
TARGET READY TRDY as an output indicates the target’s ability to complete
the current data phase of the transaction TRDY is used in conjunction with
IRDY A data phase is completed on any clock that both TRDY and IRDY are
sampled asserted When PCEB is the target during a read cycle TRDY indicates
that the PCEB has valid data present on AD 31 0 During a write it indicates that the
PCEB as a target is prepared to latch data TRDY is an input to the PCEB when
the PCEB is the initiator During reset this signal is tri-stated
sts
INITIATOR READY IRDY as an output indicates the initiator’s ability to complete
the current data phase of the transaction IRDY is used in conjunction with
TRDY A data phase is completed on any clock that both IRDY and TRDY are
sampled asserted When PCEB is the initiator of a write cycle IRDY indicates that
the PCEB has valid data present on AD 31 0 During a read it indicates the PCEB is
prepared to latch data IRDY is an input to the PCEB when the PCEB is the target
During reset this signal is tri-stated
sts
STOP As a target the PCEB asserts STOP to request that the master stop the
current transaction When the PCEB is an initiator STOP is an input As an initiator
the PCEB stops the current transaction when STOP is asserted Different
semantics of the STOP signal are defined in the context of other handshake
signals (TRDY and DEVSEL ) During reset this signal is tri-stated
sts
PCI LOCK PLOCK indicates an atomic operation that may require multiple
transactions to complete PLOCK is an input when PCEB is the target and output
when PCEB is the initiator When PLOCK is sampled negated during the address
phase of a transaction a PCI agent acting as a target will consider itself a locked
resource until it samples PLOCK and FRAME negated When other masters
attempt accesses to the PCEB (practically to the EISA subsystem) while the PCEB is
locked the PCEB responds with a retry termination During reset this signal is tri-
stated
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